From: Thomas Diener dietho@gmx.de
Signed-off-by: Thomas Diener dietho@gmx.de --- arch/arm/include/asm/arch-mx25/imx-regs.h | 271 ++++++++++++++++++++++++++++- 1 file changed, 264 insertions(+), 7 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index a17f828..dc9a298 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -161,6 +161,126 @@ struct aips_regs { u32 mpr_0_7; u32 mpr_8_15; }; +/* LCD controller registers */ +struct lcdc_regs { + u32 lssar; /* Screen Start Address */ + u32 lsr; /* Size */ + u32 lvpwr; /* Virtual Page Width */ + u32 lcpr; /* Cursor Position */ + u32 lcwhb; /* Cursor Width Height and Blink */ + u32 lccmr; /* Color Cursor Mapping */ + u32 lpcr; /* Panel Configuration */ + u32 lhcr; /* Horizontal Configuration */ + u32 lvcr; /* Vertical Configuration */ + u32 lpor; /* Panning Offset */ + u32 lscr; /* Sharp Configuration */ + u32 lpccr; /* PWM Contrast Control */ + u32 ldcr; /* DMA Control */ + u32 lrmcr; /* Refresh Mode Control */ + u32 licr; /* Interrupt Configuration */ + u32 lier; /* Interrupt Enable */ + u32 lisr; /* Interrupt Status */ + u32 res0[3]; + u32 lgwsar; /* Graphic Window Start Address */ + u32 lgwsr; /* Graphic Window Size */ + u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */ + u32 lgwpor; /* Graphic Window Panning Offset */ + u32 lgwpr; /* Graphic Window Position */ + u32 lgwcr; /* Graphic Window Control */ + u32 lgwdcr; /* Graphic Window DMA Control */ + u32 res1[5]; + u32 lauscr; /* AUS Mode Control */ + u32 lausccr; /* AUS mode Cursor Control */ + u32 res2[31 + 64*7]; + u32 bglut; /* Background Lookup Table */ + u32 gwlut; /* Graphic Window Lookup Table */ +}; + +/* Wireless External Interface Module Registers */ +struct weim_regs { + u32 cscr0u; /* Chip Select 0 Upper Register */ + u32 cscr0l; /* Chip Select 0 Lower Register */ + u32 cscr0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cscr1u; /* Chip Select 1 Upper Register */ + u32 cscr1l; /* Chip Select 1 Lower Register */ + u32 cscr1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cscr2u; /* Chip Select 2 Upper Register */ + u32 cscr2l; /* Chip Select 2 Lower Register */ + u32 cscr2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cscr3u; /* Chip Select 3 Upper Register */ + u32 cscr3l; /* Chip Select 3 Lower Register */ + u32 cscr3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cscr4u; /* Chip Select 4 Upper Register */ + u32 cscr4l; /* Chip Select 4 Lower Register */ + u32 cscr4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cscr5u; /* Chip Select 5 Upper Register */ + u32 cscr5l; /* Chip Select 5 Lower Register */ + u32 cscr5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 wcr; /* WEIM Configuration Register */ +}; + +/* Multi-Master Memory Interface */ +struct m3if_regs { + u32 ctl; /* Control Register */ + u32 wcfg0; /* Watermark Configuration Register 0 */ + u32 wcfg1; /* Watermark Configuration Register1 */ + u32 wcfg2; /* Watermark Configuration Register2 */ + u32 wcfg3; /* Watermark Configuration Register 3 */ + u32 wcfg4; /* Watermark Configuration Register 4 */ + u32 wcfg5; /* Watermark Configuration Register 5 */ + u32 wcfg6; /* Watermark Configuration Register 6 */ + u32 wcfg7; /* Watermark Configuration Register 7 */ + u32 wcsr; /* Watermark Control and Status Register */ + u32 scfg0; /* Snooping Configuration Register 0 */ + u32 scfg1; /* Snooping Configuration Register 1 */ + u32 scfg2; /* Snooping Configuration Register 2 */ + u32 ssr0; /* Snooping Status Register 0 */ + u32 ssr1; /* Snooping Status Register 1 */ + u32 res0; + u32 mlwe0; /* Master Lock WEIM CS0 Register */ + u32 mlwe1; /* Master Lock WEIM CS1 Register */ + u32 mlwe2; /* Master Lock WEIM CS2 Register */ + u32 mlwe3; /* Master Lock WEIM CS3 Register */ + u32 mlwe4; /* Master Lock WEIM CS4 Register */ + u32 mlwe5; /* Master Lock WEIM CS5 Register */ +}; + +/* Pulse width modulation */ +struct pwm_regs { + u32 cr; /* Control Register */ + u32 sr; /* Status Register */ + u32 ir; /* Interrupt Register */ + u32 sar; /* Sample Register */ + u32 pr; /* Period Register */ + u32 cnr; /* Counter Register */ +}; + +/* Enhanced Periodic Interrupt Timer */ +struct epit_regs { + u32 cr; /* Control register */ + u32 sr; /* Status register */ + u32 lr; /* Load register */ + u32 cmpr; /* Compare register */ + u32 cnr; /* Counter register */ +}; + +/* CSPI registers */ +struct cspi_regs { + u32 rxdata; + u32 txdata; + u32 ctrl; + u32 intr; + u32 dma; + u32 stat; + u32 period; + u32 test; +};
#endif
@@ -255,6 +375,7 @@ struct aips_regs { #define IMX_SDRAM_BANK0_BASE (0x80000000) #define IMX_SDRAM_BANK1_BASE (0x90000000)
+/* WEIM Memory Space */ #define IMX_WEIM_CS0 (0xA0000000) #define IMX_WEIM_CS1 (0xA8000000) #define IMX_WEIM_CS2 (0xB0000000) @@ -270,25 +391,69 @@ struct aips_regs { #define NFC_BASE_ADDR IMX_NFC_BASE
/* CCM bitfields */ +#define CCM_PLL_PD_SHIFT 26 +#define CCM_PLL_PD_MASK 0xf +#define CCM_PLL_PD(x) (((x) & CCM_PLL_PD_MASK) << CCM_PLL_PD_SHIFT) +#define CCM_PLL_MFD_SHIFT 16 +#define CCM_PLL_MFD_MASK 0x3ff +#define CCM_PLL_MFD(x) (((x) & CCM_PLL_MFD_MASK) << CCM_PLL_MFD_SHIFT) +#define CCM_PLL_LOCK (1 << 15) #define CCM_PLL_MFI_SHIFT 10 #define CCM_PLL_MFI_MASK 0xf +#define CCM_PLL_MFI(x) (((x) & CCM_PLL_MFI_MASK) << CCM_PLL_MFI_SHIFT) #define CCM_PLL_MFN_SHIFT 0 #define CCM_PLL_MFN_MASK 0x3ff -#define CCM_PLL_MFD_SHIFT 16 -#define CCM_PLL_MFD_MASK 0x3ff -#define CCM_PLL_PD_SHIFT 26 -#define CCM_PLL_PD_MASK 0xf +#define CCM_PLL_MFN(x) (((x) & CCM_PLL_MFN_MASK) << CCM_PLL_MFN_SHIFT) + +#define CCM_UPCTL_PD_SHIFT 26 +#define CCM_UPCTL_PD_MASK 0xf +#define CCM_UPCTL_PD(x) (((x) & CCM_PLL_PD_MASK) << CCM_PLL_PD_SHIFT) +#define CCM_UPCTL_MFD_SHIFT 16 +#define CCM_UPCTL_MFD_MASK 0x3ff +#define CCM_UPCTL_MFD(x) (((x) & CCM_PLL_MFD_MASK) << CCM_PLL_MFD_SHIFT) +#define CCM_UPCTL_LOCK (1 << 15) +#define CCM_UPCTL_MFI_SHIFT 10 +#define CCM_UPCTL_MFI_MASK 0xf +#define CCM_UPCTL_MFI(x) (((x) & CCM_PLL_MFI_MASK) << CCM_PLL_MFI_SHIFT) +#define CCM_UPCTL_MFN_SHIFT 0 +#define CCM_UPCTL_MFN_MASK 0x3ff +#define CCM_UPCTL_MFN(x) (((x) & CCM_PLL_MFN_MASK) << CCM_PLL_MFN_SHIFT) + #define CCM_CCTL_ARM_DIV_SHIFT 30 -#define CCM_CCTL_ARM_DIV_MASK 3 +#define CCM_CCTL_ARM_DIV_MASK 0x3 #define CCM_CCTL_AHB_DIV_SHIFT 28 -#define CCM_CCTL_AHB_DIV_MASK 3 -#define CCM_CCTL_ARM_SRC (1 << 14) +#define CCM_CCTL_AHB_DIV_MASK 0x3 +#define CCM_CCTL_AHB_DIV(x) (((x) & CCM_CCTL_AHB_DIV_MASK) << \ + CCM_CCTL_AHB_DIV_SHIFT) +#define CCM_CCTL_MPLL_RST_SHIFT 27 +#define CCM_CCTL_MPLL_RST_MASK 0x1 +#define CCM_CCTL_UPLL_RST_SHIFT 26 +#define CCM_CCTL_UPLL_RST_MASK 0x1 +#define CCM_CCTL_LP_CTL_SHIFT 24 +#define CCM_CCTL_LP_CTL_MASK 0x3 + +#define CCM_CCTL_MPLL_BYP_SHIFT 22 +#define CCM_CCTL_MPLL_BYP_MASK 0x1 +#define CCM_CCTL_USB_DIV_SHIFT 16 +#define CCM_CCTL_USB_DIV_MASK 0x3f +#define CCM_CCTL_USB_DIV(x) (((x) & CCM_CCTL_USB_DIV_MASK) << \ + CCM_CCTL_USB_DIV_SHIFT) +#define CCM_CCTL_ARM_SRC_SHIFT 14 +#define CCM_CCTL_ARM_SRC_MASK 1 +#define CCM_CCTL_ARM_SRC (1 << CCM_CCTL_ARM_SRC_SHIFT) #define CCM_CGR1_GPT1 (1 << 19) #define CCM_PERCLK_REG(clk) (clk / 4) #define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4)) #define CCM_PERCLK_MASK 0x3f #define CCM_RCSR_NF_16BIT_SEL (1 << 14) #define CCM_RCSR_NF_PS(v) ((v >> 26) & 3) +#define CCM_CRDR_BT_UART_SRC_SHIFT 29 +#define CCM_CRDR_BT_UART_SRC_MASK 7 + +#define CCM_MCR_CLKO_SEL(x) (((x) & 0xf) << 20) +#define CCM_MCR_CLKO_DIV(x) (((x) & 0x3f) << 24) +#define CCM_MCR_CLKO_EN (1 << 30) +
/* ESDRAM Controller register bitfields */ #define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) @@ -345,14 +510,106 @@ struct aips_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA
+/* MAX bits */ +#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0) + +/* M3IF bits */ +#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0) + +/* WEIM bits */ +/* The upper CS control register */ +#define WEIM_CSCR_U_SP (1 << 31) +#define WEIM_CSCR_U_WP (1 << 30) +#define WEIM_CSCR_U_BCD(x) (((x) & 0x3) << 28) +#define WEIM_CSCR_U_BCS(x) (((x) & 0xf) << 24) +#define WEIM_CSCR_U_PSZ(x) (((x) & 0x3) << 22) +#define WEIM_CSCR_U_PME (1 << 21) +#define WEIM_CSCR_U_SYNC (1 << 20) +#define WEIM_CSCR_U_DOL(x) (((x) & 0xf) << 16) +#define WEIM_CSCR_U_CNC(x) (((x) & 0x3) << 14) +#define WEIM_CSCR_U_WSC(x) (((x) & 0x3f) << 8) +#define WEIM_CSCR_U_EW (1 << 7) +#define WEIM_CSCR_U_WWS(x) (((x) & 0x7) << 4) +#define WEIM_CSCR_U_EDC(x) (((x) & 0xf) << 0) + +/* The lower CS control register */ +#define WEIM_CSCR_L_OAE(x) (((x) & 0xf) << 28) +#define WEIM_CSCR_L_OEN(x) (((x) & 0xf) << 24) +#define WEIM_CSCR_L_EBWA(x) (((x) & 0xf) << 20) +#define WEIM_CSCR_L_EBWN(x) (((x) & 0xf) << 16) +#define WEIM_CSCR_L_CSA(x) (((x) & 0xf) << 12) +#define WEIM_CSCR_L_EBC (1 << 11) +#define WEIM_CSCR_L_DSZ(x) (((x) & 0x7) << 8) +#define WEIM_CSCR_L_CSN(x) (((x) & 0xf) << 4) +#define WEIM_CSCR_L_PSR (1 << 3) +#define WEIM_CSCR_L_CRE (1 << 2) +#define WEIM_CSCR_L_WRAP (1 << 1) +#define WEIM_CSCR_L_CS_EN (1 << 0) + +/* The additional CS control register */ +#define WEIM_CSCR_A_EBRA(x) (((x) & 0xf) << 28) +#define WEIM_CSCR_A_EBRN(x) (((x) & 0xf) << 24) +#define WEIM_CSCR_A_RWA(x) (((x) & 0xf) << 20) +#define WEIM_CSCR_A_RWN(x) (((x) & 0xf) << 16) +#define WEIM_CSCR_A_MUM (1 << 15) +#define WEIM_CSCR_A_LAH(x) (((x) & 0x3) << 13) +#define WEIM_CSCR_A_LBN(x) (((x) & 0x7) << 10) +#define WEIM_CSCR_A_LBA(x) (((x) & 0x3) << 8) +#define WEIM_CSCR_A_DWW(x) (((x) & 0x3) << 6) +#define WEIM_CSCR_A_DCT(x) (((x) & 0x3) << 4) +#define WEIM_CSCR_A_WWU (1 << 3) +#define WEIM_CSCR_A_AGE (1 << 2) +#define WEIM_CSCR_A_CNC2 (1 << 1) +#define WEIM_CSCR_A_FCE (1 << 0) + /* Names used in GPIO driver */ #define GPIO1_BASE_ADDR IMX_GPIO1_BASE #define GPIO2_BASE_ADDR IMX_GPIO2_BASE #define GPIO3_BASE_ADDR IMX_GPIO3_BASE #define GPIO4_BASE_ADDR IMX_GPIO4_BASE
+/* + * CSPI register definitions + */ +#define MXC_CSPI +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) +#define MXC_CSPICTRL_TC (1 << 7) +#define MXC_CSPICTRL_RXOVF (1 << 6) +#define MXC_CSPICTRL_MAXBITS 0xfff +#define MXC_CSPIPERIOD_32KHZ (1 << 15) +#define MAX_SPI_BYTES 4 + +#define MXC_SPI_BASE_ADDRESSES \ + IMX_CSPI1_BASE, \ + IMX_CSPI2_BASE, \ + IMX_CSPI3_BASE + #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_1 0x11 #define CHIP_REV_1_2 0x12
+/* EPIT bitfields */ +#define EPIT_CR_EN (1 << 0) +#define EPIT_CR_RLD (1 << 3) +#define EPIT_CR_IOVW (1 << 17) +#define EPIT_CR_OM(x) (((x) & 0x3) << 22) +#define EPIT_CR_CLKSRC(x) (((x) & 0x3) << 24) +#define EPIT_LR(x) (((x) & 0xFFFFFFFF) << 0) +#define EPIT_CMPR(x) (((x) & 0xFFFFFFFF) << 0) + +/* PWM bitfields */ +#define PWM_CR_EN (1 << 0) +#define PWM_CR_CLKSRC(x) (((x) & 0x3) << 16) +#define PWM_CR_POUTC(x) (((x) & 0x3) << 18) + #endif /* _IMX_REGS_H */