Add initial clock driver for Allwinner A23/A33.
- Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c
Signed-off-by: Jagan Teki jagan@amarulasolutions.com Acked-by: Maxime Ripard maxime.ripard@bootlin.com --- drivers/clk/sunxi/Kconfig | 7 +++++ drivers/clk/sunxi/Makefile | 1 + drivers/clk/sunxi/clk_a23.c | 63 +++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) create mode 100644 drivers/clk/sunxi/clk_a23.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index 535b0dc02c..38ff99d345 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -30,6 +30,13 @@ config CLK_SUN6I_A31 This enables common clock driver support for platforms based on Allwinner A31/A31s SoC.
+config CLK_SUN8I_A23 + bool "Clock driver for Allwinner A23/A33" + default MACH_SUN8I_A23 || MACH_SUN8I_A33 + help + This enables common clock driver support for platforms based + on Allwinner A23/A33 SoC. + config CLK_SUN8I_H3 bool "Clock driver for Allwinner H3/H5" default MACH_SUNXI_H3_H5 diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile index 3cf0071b0c..6924897036 100644 --- a/drivers/clk/sunxi/Makefile +++ b/drivers/clk/sunxi/Makefile @@ -9,5 +9,6 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sunxi.o obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o +obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c new file mode 100644 index 0000000000..2a504ebdad --- /dev/null +++ b/drivers/clk/sunxi/clk_a23.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2018 Amarula Solutions B.V. + * Author: Jagan Teki jagan@amarulasolutions.com + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <asm/arch/ccu.h> +#include <dt-bindings/clock/sun8i-a23-a33-ccu.h> +#include <dt-bindings/reset/sun8i-a23-a33-ccu.h> + +static struct ccu_clk_gate a23_gates[] = { + [CLK_BUS_OTG] = GATE(0x060, BIT(24)), + [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), + [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), + + [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), + [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)), + [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)), + [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)), + [CLK_USB_OHCI] = GATE(0x0cc, BIT(16)), +}; + +static struct ccu_reset a23_resets[] = { + [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), + [RST_USB_PHY1] = RESET(0x0cc, BIT(1)), + [RST_USB_HSIC] = RESET(0x0cc, BIT(2)), + + [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), + [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)), + [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)), +}; + +static const struct ccu_desc a23_ccu_desc = { + .gates = a23_gates, + .resets = a23_resets, +}; + +static int a23_clk_bind(struct udevice *dev) +{ + return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets)); +} + +static const struct udevice_id a23_clk_ids[] = { + { .compatible = "allwinner,sun8i-a23-ccu", + .data = (ulong)&a23_ccu_desc }, + { .compatible = "allwinner,sun8i-a33-ccu", + .data = (ulong)&a23_ccu_desc }, + { } +}; + +U_BOOT_DRIVER(clk_sun8i_a23) = { + .name = "sun8i_a23_ccu", + .id = UCLASS_CLK, + .of_match = a23_clk_ids, + .priv_auto_alloc_size = sizeof(struct ccu_priv), + .ops = &sunxi_clk_ops, + .probe = sunxi_clk_probe, + .bind = a23_clk_bind, +};