Signed-off-by: Remy Bohmer linux@bohmer.net --- V2 reworked comments from Jean-Christophe PLAGNIOL-VILLARD
cpu/arm926ejs/at91/Makefile | 1 + cpu/arm926ejs/at91/cpuinfo.c | 65 +++++++++++++++++++++ include/asm-arm/arch-at91/at91_dbgu.h | 69 +++++++++++++++++++++++ include/asm-arm/arch-at91/cpu.h | 99 +++++++++++++++++++++++++++++++++ 4 files changed, 234 insertions(+), 0 deletions(-) create mode 100644 cpu/arm926ejs/at91/cpuinfo.c create mode 100644 include/asm-arm/arch-at91/at91_dbgu.h create mode 100644 include/asm-arm/arch-at91/cpu.h
diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 71acb0b..5c970a1 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91_LED) += led.o +COBJS-$(CONFIG_DISPLAY_CPUINFO) +=cpuinfo.o COBJS-y += clock.o COBJS-y += cpu.o COBJS-y += timer.o diff --git a/cpu/arm926ejs/at91/cpuinfo.c b/cpu/arm926ejs/at91/cpuinfo.c new file mode 100644 index 0000000..1c6abad --- /dev/null +++ b/cpu/arm926ejs/at91/cpuinfo.c @@ -0,0 +1,65 @@ +#include <command.h> +#include <common.h> +#include <arm926ejs.h> +#include <asm/hardware.h> +#include <asm/arch/at91_dbgu.h> +#include <asm/arch/io.h> + +int print_cpuinfo(void) +{ + unsigned long cidr; + const char *txt; + + cidr = at91_sys_read(AT91_DBGU_CIDR); + + switch ((cidr & AT91_CIDR_EPROC) >> 5) { + /* 0x1 = ARM946ES, 0x2 = ARM7TDMI, 0x4 = ARM920T */ + case 0x5: txt = "ARM926EJS"; break; + default: txt = "undefined"; break; + } + printf("Embedded Processor: %s\n", txt); + + switch ((cidr & AT91_CIDR_ARCH) >> 20) { + case 0x19: txt = "AT91SAM9xx"; break; + case 0x29: txt = "AT91SAM9XExx"; break; + case 0x39: txt = "CAP9"; break; + default: txt = "undefined"; break; + } + printf("Architecture: %s Series\n", txt); + + printf("CPU-revision: %c\n", (char)('A' + (cidr & AT91_CIDR_VERSION))); + + switch ((cidr & AT91_CIDR_NVPTYP) >> 28) { + case 0x0: txt = "ROM"; break; + case 0x1: txt = "ROMless or onchip flash"; break; + case 0x2: txt = "Embedded flash memory"; break; + case 0x3: txt = "ROM and Embedded flash memory"; break; + case 0x4: txt = "SRAM emulating ROM"; break; + default: txt = "undefined"; break; + } + printf("NonVolatile Program Memory type: %s\n", txt); + + switch (cidr & AT91_CIDR_SRAMSIZ) { + case AT91_CIDR_SRAMSIZ_1K: txt = "1K"; break; + case AT91_CIDR_SRAMSIZ_2K: txt = "2K"; break; + case AT91_CIDR_SRAMSIZ_112K: txt = "112K"; break; + case AT91_CIDR_SRAMSIZ_4K: txt = "4K"; break; + case AT91_CIDR_SRAMSIZ_80K: txt = "80K"; break; + case AT91_CIDR_SRAMSIZ_160K: txt = "160K"; break; + case AT91_CIDR_SRAMSIZ_8K: txt = "8K"; break; + case AT91_CIDR_SRAMSIZ_16K: txt = "16K"; break; + case AT91_CIDR_SRAMSIZ_32K: txt = "32K"; break; + case AT91_CIDR_SRAMSIZ_64K: txt = "64K"; break; + case AT91_CIDR_SRAMSIZ_128K: txt = "128K"; break; + case AT91_CIDR_SRAMSIZ_256K: txt = "256K"; break; + case AT91_CIDR_SRAMSIZ_96K: txt = "96K"; break; + case AT91_CIDR_SRAMSIZ_512K: txt = "512K"; break; + default: txt = "undefined"; break; + } + printf("Internal SRAM size: %s\n", txt); + + if (cidr & AT91_CIDR_EXT) + printf("Extension ID: 0x%x\n", at91_sys_read(AT91_DBGU_EXID)); + + return 0; +} diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h new file mode 100644 index 0000000..55210da --- /dev/null +++ b/include/asm-arm/arch-at91/at91_dbgu.h @@ -0,0 +1,69 @@ +/* + * include/asm-arm/arch-at91/at91_dbgu.h + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Debug Unit (DBGU) - System peripherals registers. + * Based on AT91RM9200 datasheet revision E. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBGU_H +#define AT91_DBGU_H + +#ifdef AT91_DBGU +#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ +#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ +#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable */ +#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ +#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ +#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable */ +#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask */ +#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ +#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding */ +#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding */ +#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator */ + +#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ +#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension */ +#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST [SAM9 only] */ +#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ + +#endif /* AT91_DBGU */ + +/* + * Some AT91 parts that don't have full DEBUG units still support the ID + * and extensions register. + */ +#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ +#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ +#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program + Memory Size */ +#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile + Program Memory Size */ +#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ +#define AT91_CIDR_SRAMSIZ_1K (1 << 16) +#define AT91_CIDR_SRAMSIZ_2K (2 << 16) +#define AT91_CIDR_SRAMSIZ_112K (4 << 16) +#define AT91_CIDR_SRAMSIZ_4K (5 << 16) +#define AT91_CIDR_SRAMSIZ_80K (6 << 16) +#define AT91_CIDR_SRAMSIZ_160K (7 << 16) +#define AT91_CIDR_SRAMSIZ_8K (8 << 16) +#define AT91_CIDR_SRAMSIZ_16K (9 << 16) +#define AT91_CIDR_SRAMSIZ_32K (10 << 16) +#define AT91_CIDR_SRAMSIZ_64K (11 << 16) +#define AT91_CIDR_SRAMSIZ_128K (12 << 16) +#define AT91_CIDR_SRAMSIZ_256K (13 << 16) +#define AT91_CIDR_SRAMSIZ_96K (14 << 16) +#define AT91_CIDR_SRAMSIZ_512K (15 << 16) +#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Id */ +#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program + Memory Type */ +#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ + +#endif diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h new file mode 100644 index 0000000..b5e5715 --- /dev/null +++ b/include/asm-arm/arch-at91/cpu.h @@ -0,0 +1,99 @@ +/* + * include/asm-arm/arch-at91/cpu.h + * + * Copyright (C) 2006 SAN People + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_CPU_H +#define __ASM_ARCH_CPU_H + +#include <asm/hardware.h> +#include <asm/arch/at91_dbgu.h> +#include <asm/arch/io.h> + + +#define ARCH_ID_AT91RM9200 0x09290780 +#define ARCH_ID_AT91SAM9260 0x019803a0 +#define ARCH_ID_AT91SAM9261 0x019703a0 +#define ARCH_ID_AT91SAM9263 0x019607a0 +#define ARCH_ID_AT91SAM9RL64 0x019b03a0 +#define ARCH_ID_AT91CAP9 0x039A03A0 + +#define ARCH_ID_AT91SAM9XE128 0x329973a0 +#define ARCH_ID_AT91SAM9XE256 0x329a93a0 +#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 + +#define ARCH_ID_AT91M40800 0x14080044 +#define ARCH_ID_AT91R40807 0x44080746 +#define ARCH_ID_AT91M40807 0x14080745 +#define ARCH_ID_AT91R40008 0x44000840 + +static inline unsigned long at91_cpu_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); +} + + +#define ARCH_FAMILY_AT91X92 0x09200000 +#define ARCH_FAMILY_AT91SAM9 0x01900000 +#define ARCH_FAMILY_AT91SAM9XE 0x02900000 + +static inline unsigned long at91_arch_identify(void) +{ + return (at91_sys_read(AT91_DBGU_CIDR) & AT91_CIDR_ARCH); +} + + +#ifdef CONFIG_AT91RM9200 +/* no actual detection for this architecture */ +#define cpu_is_at91rm9200() (1) +#else +#define cpu_is_at91rm9200() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9xe() (at91_arch_identify() == ARCH_FAMILY_AT91SAM9XE) +#define cpu_is_at91sam9260() ((at91_cpu_identify() == ARCH_ID_AT91SAM9260) \ + || cpu_is_at91sam9xe()) +#else +#define cpu_is_at91sam9xe() (0) +#define cpu_is_at91sam9260() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) +#else +#define cpu_is_at91sam9261() (0) +#endif + +#ifdef CONFIG_AT91SAM9261 +#define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) +#else +#define cpu_is_at91sam9263() (0) +#endif + +#ifdef CONFIG_AT91SAM9RL +#define cpu_is_at91sam9rl() (at91_cpu_identify() == ARCH_ID_AT91SAM9RL64) +#else +#define cpu_is_at91sam9rl() (0) +#endif + +#ifdef CONFIG_AT91CAP9 +#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) +#else +#define cpu_is_at91cap9() (0) +#endif + +/* + * Since this is ARM, we will never run on any AVR32 CPU. But these + * definitions may reduce clutter in common drivers. + */ +#define cpu_is_at32ap7000() (0) + +#endif