Marek,
Am 12.11.2019 um 12:57 schrieb Simon Goldschmidt:
On Tue, Nov 12, 2019 at 12:40 PM Vignesh Raghavendra vigneshr@ti.com wrote:
On 12/11/19 4:57 PM, Simon Goldschmidt wrote:
On Tue, Nov 12, 2019 at 10:30 AM Tan, Ley Foon ley.foon.tan@intel.com wrote:
[...]
But, unfortunately, such stub does not exists for clk_get_rate(). So on platforms w/o CONFIG_CLK set:
arm-linux-gnueabihf-ld.bfd: drivers/spi/built-in.o: in function
`cadence_spi_probe':
/home/a0132425/workspace/u-boot/drivers/spi/cadence_qspi.c:184:
undefined reference to `clk_get_rate'
Makefile:1647: recipe for target 'u-boot' failed make: *** [u-boot] Error 1
So why did it compile for me? Probably because the linker knows it doesn't need 'clk_get_rate' since this branch will never be executed?
Maybe you can try compile from clean build. Run "make mrproper" before compile.
Of course I did that, and I just did it again. It *does* compile.
Can anyone tell me a config/setup where it doesn't compile? Or does this complain only come from reading the sources?
I see above error with k2g_evm_defconfig and compiler is:
Ok, just tested that config and it works for me :-(
After having a successful travis run for this on top of u-boot-socfpga/master, could you take this and re-send the PR of last week?
Travis run is here:
https://travis-ci.org/goldsimon/u-boot/builds/614187977
Regards, Simon
arm-linux-gnueabihf-gcc (GNU Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36)) 8.3.0
I'm using 6.3.0 from debian stretch, but have also tested my patch with newest Ubuntu (which has a 9.x cross compiler).
So while I think that difference is disturbing, Maybe it's really best to inline-define all clock functions as you mentioned to Patrick in the other thread...
Regards, Simon
Regards Vignesh
Regards, Simon
Regards Ley Foon
Regards, Simon
Regards Vignesh
> That should be enough, no? And yes, I did test this on the current > state of > gen5 which does not have a CLK driver, yet. > > Regards, > Simon > >> >> Regards >> Ley Foon >> >>> + ret = clk_get_by_index(bus, 0, &clk); >>> + if (ret) { >>> +#ifdef CONFIG_CQSPI_REF_CLK >>> + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; #else >>> + return ret; >>> +#endif >>> + } else { >>> + plat->ref_clk_hz = clk_get_rate(&clk); >>> + clk_free(&clk); >>> + if (IS_ERR_VALUE(plat->ref_clk_hz)) >>> + return plat->ref_clk_hz; >>> + } >>> + >>> debug("%s: regbase=%p ahbbase=%p max-frequency=%d page- >>> size=%d\n", >>> __func__, plat->regbase, plat->ahbbase, plat->max_hz, >>> plat->page_size); >>> diff --git a/drivers/spi/cadence_qspi.h >>> b/drivers/spi/cadence_qspi.h index 20cceca239..99dee75bbd 100644 >>> --- a/drivers/spi/cadence_qspi.h >>> +++ b/drivers/spi/cadence_qspi.h >>> @@ -16,6 +16,7 @@ >>> #define CQSPI_READ_CAPTURE_MAX_DELAY 16 >>> >>> struct cadence_spi_platdata { >>> + unsigned int ref_clk_hz; >>> unsigned int max_hz; >>> void *regbase; >>> void *ahbbase; >>> -- >>> 2.20.1 >>
-- Regards Vignesh