In Commit d64077202158 ("spi: cadence_qspi: Move to spi-mem framework") it removes setting to quad write bit by accident. This commit restores it back and also adding checking for octal support.
Fixes: d64077202158 ("spi: cadence_qspi: Move to spi-mem framework")
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- drivers/spi/cadence_qspi_apb.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index f9675f75a401..aaf5f600c6dc 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -689,6 +689,12 @@ int cadence_qspi_apb_write_setup(struct cadence_spi_platdata *plat,
/* Configure the opcode */ reg = op->cmd.opcode << CQSPI_REG_WR_INSTR_OPCODE_LSB; + + if (op->data.buswidth == 8) + reg |= CQSPI_INST_TYPE_OCTAL << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + else if (op->data.buswidth == 4) + reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; + writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
writel(op->addr.val, plat->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);