Hi,
-----Original Message----- From: Jagan Teki [mailto:jagannadh.teki@gmail.com] Sent: Tuesday, May 29, 2018 10:22 AM To: Marek Vasut marex@denx.de; Siva Durga Prasad Paladugu sivadur@xilinx.com Cc: U-Boot Mailing List u-boot@lists.denx.de; Tom Rini trini@konsulko.com Subject: Re: [U-Boot] [PATCH] sf: Enable FSR polling on N25Q256(A)
- Siva
On Fri, May 25, 2018 at 1:28 AM, Marek Vasut marex@denx.de wrote:
The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption.
Signed-off-by: Marek Vasut marex@denx.de Cc: Jagan Teki jagan@openedev.com Cc: Tom Rini trini@konsulko.com
drivers/mtd/spi/spi_flash_ids.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c index 3b8f254ca2..fbc1bb6a5e 100644 --- a/drivers/mtd/spi/spi_flash_ids.c +++ b/drivers/mtd/spi/spi_flash_ids.c @@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = { {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL |
WR_QPP | SECT_4K) },
{"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL |WR_QPP) },
{"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL |WR_QPP) },
{"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL |WR_QPP | SECT_4K) },
{"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL |WR_QPP | SECT_4K) },
{"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL |WR_QPP | E_FSR | SECT_4K) },
{"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL |WR_QPP | E_FSR | SECT_4K) },
FSR is required to poll flag status instead of read status only from Micron n25q512 because 512 is divided into two 256 dies so FSR is used for polling each die. In case of n25q256 the flash is single entity (doesn't have die concept) so there is no need to poll FSR.
This is what I understood when I add initial FSR support 0f6232801cee4f45dbdb0cec45f71172c9b617ca
PEC bit in Flag status register on N25Q256A will apply only for PROGRAM/ERASE commands but not to WRITE command cycles where as WIP bit in Status register will be applicable to all(PROGRAM/ERASE and WRITE). Here is the snippet from N25Q256A datasheet about PEC bit in FSR. "These program/erase controller settings apply only to PROGRAM or ERASE command cycles in progress; they do not apply to a WRITE command cycle in progress."
Regarding PEC bit in FSR of N25Q512(where it has two 256MB dies) here, it is mostly used to find out whether WRITE command(Write Status and Write Non volatile config Register) completed successfully for both dies. This is ensured by reading FSR twice with S# toggled in between and checking the PEC bit to be 1 in both the cases.
Thanks, Siva
Jagan.
-- Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.