The LS1043ARDB rev v7.0 board replace nand device MT29F4G08ABBDAH4-AITX:D with MT29F4G08ABBFAH4-AIT:F. Reflecting this change in board_fix_fdt(). CPLD V3.0 is needed for nandboot as the nand device changed. A new macro CPLD_CFG_RCW_SRC_NAND_4K(4Kpage) is added to distinguish from CPLD_CFG_RCW_SRC_NAND(2Kpage) to support nandboot on rev v7.0 board.
Signed-off-by: Wei Lu w.lu@nxp.com --- board/freescale/ls1043ardb/cpld.c | 4 +++ board/freescale/ls1043ardb/cpld.h | 1 + board/freescale/ls1043ardb/ls1043ardb.c | 46 ++++++++++++++++++++++++- 3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/board/freescale/ls1043ardb/cpld.c b/board/freescale/ls1043ardb/cpld.c index 5d2e8015a0..232035638b 100644 --- a/board/freescale/ls1043ardb/cpld.c +++ b/board/freescale/ls1043ardb/cpld.c @@ -69,6 +69,10 @@ void cpld_set_defbank(void) void cpld_set_nand(void) { u16 reg = CPLD_CFG_RCW_SRC_NAND; + + if (CPLD_READ(cpld_ver) > 0x2) + reg = CPLD_CFG_RCW_SRC_NAND_4K; + u8 reg5 = (u8)(reg >> 1); u8 reg6 = (u8)(reg & 1);
diff --git a/board/freescale/ls1043ardb/cpld.h b/board/freescale/ls1043ardb/cpld.h index 2e757b557f..eed34d6354 100644 --- a/board/freescale/ls1043ardb/cpld.h +++ b/board/freescale/ls1043ardb/cpld.h @@ -41,5 +41,6 @@ void cpld_rev_bit(unsigned char *value); #define CPLD_BANK_SEL_ALTBANK 0x04 #define CPLD_CFG_RCW_SRC_NOR 0x025 #define CPLD_CFG_RCW_SRC_NAND 0x106 +#define CPLD_CFG_RCW_SRC_NAND_4K 0x118 #define CPLD_CFG_RCW_SRC_SD 0x040 #endif diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index f388eb496f..8c91f0771f 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -167,7 +167,7 @@ int checkboard(void)
if (cfg_rcw_src == 0x25) printf("vBank %d\n", CPLD_READ(vbank)); - else if (cfg_rcw_src == 0x106) + else if ((cfg_rcw_src == 0x106) || (cfg_rcw_src == 0x118)) puts("NAND\n"); else printf("Invalid setting of SW4\n"); @@ -347,10 +347,54 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; }
+void nand_fixup(void) +{ + u32 csor = 0; + + if (CPLD_READ(pcba_ver) < 0x7) + return; + + /* Change NAND Flash PGS/SPRZ configuration */ + csor = CONFIG_SYS_NAND_CSOR; + if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) + csor = (csor & ~(CSOR_NAND_PGS_MASK)) | CSOR_NAND_PGS_4K; + + if ((csor & CSOR_NAND_SPRZ_MASK) == CSOR_NAND_SPRZ_64) + csor = (csor & ~(CSOR_NAND_SPRZ_MASK)) | CSOR_NAND_SPRZ_224; + + if (IS_ENABLED(CONFIG_TFABOOT)) { + u8 cfg_rcw_src1, cfg_rcw_src2; + u16 cfg_rcw_src; + + cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1); + cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2); + cpld_rev_bit(&cfg_rcw_src1); + cfg_rcw_src = cfg_rcw_src1; + cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2; + + if (cfg_rcw_src == 0x25) + set_ifc_csor(IFC_CS1, csor); + else if (cfg_rcw_src == 0x118) + set_ifc_csor(IFC_CS0, csor); + else + printf("Invalid setting\n"); + } else { + if (IS_ENABLED(CONFIG_NAND_BOOT)) + set_ifc_csor(IFC_CS0, csor); + else + set_ifc_csor(IFC_CS1, csor); + } +} + #if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) int board_fix_fdt(void *blob) { + /* nand driver fix up */ + nand_fixup(); + + /* fdt fix up */ fdt_fixup_phy_addr(blob); + return 0; } #endif