Hi Prafulla,
On Fri, Oct 7, 2011 at 11:53 AM, Prafulla Wadaskar prafulla@marvell.com wrote:
-----Original Message----- From: Lei Wen [mailto:leiwen@marvell.com] Sent: Wednesday, October 05, 2011 8:43 PM To: Prafulla Wadaskar; u-boot@lists.denx.de Subject: [PATCH] ARM: pantheon: enable dcache by default
Marvell 88SV331xV5 has its specific arm cp15 opcode, which could
I think this will be applicable to all SoC those fall under this core. So we should modify arch/arm/include/asm/cache.h for this.
I modify my original one patch into three small patch series. And put the op code place as you suggested, please help re-check it.
flush out whole dcache by only one line of asm code.
Signed-off-by: Lei Wen leiwen@marvell.com
arch/arm/cpu/arm926ejs/pantheon/cpu.c | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c index 2d9c13a..8f94ea9 100644 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c @@ -105,3 +105,17 @@ void i2c_clk_enable(void) { } #endif
+#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
+}
+void flush_cache(unsigned long start, unsigned long size) +{
- /* clean & invalidate all D cache */
- asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+} +#endif
Otherwise ack for this change
Thanks, Lei