Fifo width could be different on different socs, e.g. stv0991 & altera soc have different fifo width.
Signed-off-by: Vikas Manocha vikas.manocha@st.com --- arch/arm/dts/socfpga.dtsi | 1 + arch/arm/dts/stv0991.dts | 1 + drivers/spi/cadence_qspi.c | 1 + drivers/spi/cadence_qspi.h | 1 + drivers/spi/cadence_qspi_apb.c | 13 ++++--------- 5 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi index c957f44..48bbbb3 100644 --- a/arch/arm/dts/socfpga.dtsi +++ b/arch/arm/dts/socfpga.dtsi @@ -641,6 +641,7 @@ num-cs = <4>; fifo-depth = <128>; sram-size = <128>; + fifo-width = <4>; bus-num = <2>; status = "disabled"; }; diff --git a/arch/arm/dts/stv0991.dts b/arch/arm/dts/stv0991.dts index f30a818..96583b1 100644 --- a/arch/arm/dts/stv0991.dts +++ b/arch/arm/dts/stv0991.dts @@ -37,6 +37,7 @@ num-cs = <4>; fifo-depth = <256>; sram-size = <256>; + fifo-width = <8>; bus-num = <0>; status = "okay";
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 8b6de4f..71594ed 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -311,6 +311,7 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tchsh_ns = fdtdec_get_int(blob, subnode, "tchsh-ns", 20); plat->tslch_ns = fdtdec_get_int(blob, subnode, "tslch-ns", 20); plat->sram_size = fdtdec_get_int(blob, node, "sram-size", 128); + plat->fifo_width = fdtdec_get_int(blob, node, "fifo-width", 4);
debug("%s: regbase=%p flashbase=%p trigger_base=%p max-frequency=%d \ page-size=%d\n", __func__, plat->regbase, plat->flashbase, \ diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 7341339..91f38f1 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -27,6 +27,7 @@ struct cadence_spi_platdata { u32 tchsh_ns; u32 tslch_ns; u32 sram_size; + u32 fifo_width; };
struct cadence_spi_priv { diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e6ff0e0..b37addf 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -34,8 +34,6 @@ #define CQSPI_REG_RETRY (10000) #define CQSPI_POLL_IDLE_RETRY (3)
-#define CQSPI_FIFO_WIDTH (4) - #define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */ @@ -48,9 +46,6 @@ #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4)
- -#define CQSPI_REG_SRAM_FILL_THRESHOLD \ - ((CQSPI_REG_SRAM_SIZE_WORD / 2) * CQSPI_FIFO_WIDTH) /**************************************************************************** * Controller's configuration and status register (offset from QSPI_BASE) ****************************************************************************/ @@ -229,11 +224,11 @@ static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat, page_size : remaining;
remaining -= wr_bytes; - while (wr_bytes >= CQSPI_FIFO_WIDTH) { - for (i = 0; i < CQSPI_FIFO_WIDTH/sizeof(dest_addr); i++) + while (wr_bytes >= plat->fifo_width) { + for (i = 0; i < plat->fifo_width/sizeof(dest_addr); i++) writel(*(src_ptr+i), dest_addr+i); - src_ptr += CQSPI_FIFO_WIDTH/sizeof(dest_addr); - wr_bytes -= CQSPI_FIFO_WIDTH; + src_ptr += plat->fifo_width/sizeof(dest_addr); + wr_bytes -= plat->fifo_width; } if (wr_bytes) {