This is the first ARMv8 SoC from Socionext Inc.
Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---
Changes in v2: - Enable booti command - add early_clk_init func()
arch/arm/mach-uniphier/Kconfig | 5 ++ arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/arm64/Makefile | 8 +++ arch/arm/mach-uniphier/arm64/mem_map.c | 28 +++++++++ arch/arm/mach-uniphier/board_late_init.c | 2 +- arch/arm/mach-uniphier/boards.c | 25 ++++++++ arch/arm/mach-uniphier/boot-mode/Makefile | 1 + arch/arm/mach-uniphier/boot-mode/boot-device.h | 2 + arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c | 77 +++++++++++++++++++++++ arch/arm/mach-uniphier/boot-mode/boot-mode.c | 4 ++ arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c | 5 ++ arch/arm/mach-uniphier/cpu_info.c | 2 +- arch/arm/mach-uniphier/dram/Makefile | 1 + arch/arm/mach-uniphier/dram/umc-ld20.c | 14 +++++ arch/arm/mach-uniphier/early-clk/Makefile | 1 + arch/arm/mach-uniphier/early-clk/early-clk-ld20.c | 30 +++++++++ arch/arm/mach-uniphier/init.h | 3 + arch/arm/mach-uniphier/init/Makefile | 1 + arch/arm/mach-uniphier/init/init-ld20.c | 55 ++++++++++++++++ arch/arm/mach-uniphier/init/init.c | 5 ++ arch/arm/mach-uniphier/memconf/Makefile | 1 + arch/arm/mach-uniphier/memconf/memconf-pxs2.c | 3 + arch/arm/mach-uniphier/sbc/Makefile | 1 + arch/arm/mach-uniphier/sg-regs.h | 3 +- configs/uniphier_ld20_defconfig | 28 +++++++++ include/configs/uniphier.h | 37 +++++++++-- 26 files changed, 335 insertions(+), 8 deletions(-) create mode 100644 arch/arm/mach-uniphier/arm64/Makefile create mode 100644 arch/arm/mach-uniphier/arm64/mem_map.c create mode 100644 arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c create mode 100644 arch/arm/mach-uniphier/dram/umc-ld20.c create mode 100644 arch/arm/mach-uniphier/early-clk/early-clk-ld20.c create mode 100644 arch/arm/mach-uniphier/init/init-ld20.c create mode 100644 configs/uniphier_ld20_defconfig
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 4724af5..87d1675 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -23,6 +23,11 @@ config ARCH_UNIPHIER_PRO5_PXS2_LD6B bool "UniPhier PH1-Pro5/ProXstream2/PH1-LD6b SoC" select CPU_V7
+config ARCH_UNIPHIER_LD20 + bool "UniPhier PH1-LD20 SoC" + select ARM64 + select SPL_SEPARATE_BSS + endchoice
config ARCH_UNIPHIER_LD4 diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 35edca1..774ea99 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -31,3 +31,4 @@ obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/
obj-$(CONFIG_CPU_V7) += arm32/ +obj-$(CONFIG_ARM64) += arm64/ diff --git a/arch/arm/mach-uniphier/arm64/Makefile b/arch/arm/mach-uniphier/arm64/Makefile new file mode 100644 index 0000000..3e69eab --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj- += dummy.o +ifndef CONFIG_SPL_BUILD +obj-y += mem_map.o +endif diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c new file mode 100644 index 0000000..74ef919 --- /dev/null +++ b/arch/arm/mach-uniphier/arm64/mem_map.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/types.h> +#include <asm/armv8/mmu.h> + +static struct mm_region uniphier_mem_map[] = { + { + .base = 0x00000000, + .size = 0x80000000, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, + { + .base = 0x80000000, + .size = 0xc0000000, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, + { /* sentinel */ } +}; + +struct mm_region *mem_map = uniphier_mem_map; diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 6e2008c..a440a7e 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -36,7 +36,7 @@ struct uniphier_fdt_file { static const struct uniphier_fdt_file uniphier_fdt_files[] = { { "socionext,ph1-ld4-ref", "uniphier-ph1-ld4-ref.dtb", }, { "socionext,ph1-ld6b-ref", "uniphier-ph1-ld6b-ref.dtb", }, - { "socionext,ph1-ld10-ref", "uniphier-ph1-ld10-ref.dtb", }, + { "socionext,ph1-ld20-ref", "uniphier-ph1-ld20-ref.dtb", }, { "socionext,ph1-pro4-ace", "uniphier-ph1-pro4-ace.dtb", }, { "socionext,ph1-pro4-ref", "uniphier-ph1-pro4-ref.dtb", }, { "socionext,ph1-pro4-sanji", "uniphier-ph1-pro4-sanji.dtb", }, diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index 0d2b94d..f0547c3 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -165,6 +165,28 @@ static const struct uniphier_board_data uniphier_ld6b_data = { }; #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20) +static const struct uniphier_board_data uniphier_ld20_data = { + .dram_freq = 1866, + .dram_nr_ch = 3, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[2] = { + .base = 0x100000000UL, + .size = 0x40000000, + .width = 32, + }, +}; +#endif + struct uniphier_board_id { const char *compatible; const struct uniphier_board_data *param; @@ -194,6 +216,9 @@ static const struct uniphier_board_id uniphier_boards[] = { #if defined(CONFIG_ARCH_UNIPHIER_LD6B) { "socionext,ph1-ld6b", &uniphier_ld6b_data, }, #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + { "socionext,ph1-ld20", &uniphier_ld20_data, }, +#endif };
const struct uniphier_board_data *uniphier_get_board_param(void) diff --git a/arch/arm/mach-uniphier/boot-mode/Makefile b/arch/arm/mach-uniphier/boot-mode/Makefile index 278df64..6cd096e 100644 --- a/arch/arm/mach-uniphier/boot-mode/Makefile +++ b/arch/arm/mach-uniphier/boot-mode/Makefile @@ -11,5 +11,6 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += boot-mode-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += boot-mode-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += boot-mode-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += boot-mode-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += boot-mode-ld20.o
obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o diff --git a/arch/arm/mach-uniphier/boot-mode/boot-device.h b/arch/arm/mach-uniphier/boot-mode/boot-device.h index 2e05a47..bd44d73 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-device.h +++ b/arch/arm/mach-uniphier/boot-mode/boot-device.h @@ -16,11 +16,13 @@ u32 uniphier_sld3_boot_device(void); u32 uniphier_ld4_boot_device(void); u32 uniphier_pro5_boot_device(void); u32 uniphier_pxs2_boot_device(void); +u32 uniphier_ld20_boot_device(void);
void uniphier_sld3_boot_mode_show(void); void uniphier_ld4_boot_mode_show(void); void uniphier_pro5_boot_mode_show(void); void uniphier_pxs2_boot_mode_show(void); +void uniphier_ld20_boot_mode_show(void);
u32 spl_boot_device_raw(void);
diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c new file mode 100644 index 0000000..100275e --- /dev/null +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode-ld20.c @@ -0,0 +1,77 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <linux/io.h> + +#include "../sg-regs.h" +#include "boot-device.h" + +static struct boot_device_info boot_device_table[] = { + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI, Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 4)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 8, ONFI Addr 5)"}, + {BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI Addr 5)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 8bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_MMC1, "eMMC (High Speed SDR, 8bit, 1.8V, Training On)"}, + {BOOT_DEVICE_MMC1, "eMMC (Legacy, 4bit, 1.8V, Training Off)"}, + {BOOT_DEVICE_NONE, "Reserved"}, +}; + +static int get_boot_mode_sel(void) +{ + return (readl(SG_PINMON0) >> 1) & 0x1f; +} + +u32 uniphier_ld20_boot_device(void) +{ + int boot_mode; + + if (~readl(SG_PINMON0) & 0x00000780) + return BOOT_DEVICE_USB; + + boot_mode = get_boot_mode_sel(); + + return boot_device_table[boot_mode].type; +} + +void uniphier_ld20_boot_mode_show(void) +{ + int mode_sel, i; + + mode_sel = get_boot_mode_sel(); + + puts("Boot Mode Pin:\n"); + + for (i = 0; i < ARRAY_SIZE(boot_device_table); i++) + printf(" %c %02x %s\n", i == mode_sel ? '*' : ' ', i, + boot_device_table[i].info); +} diff --git a/arch/arm/mach-uniphier/boot-mode/boot-mode.c b/arch/arm/mach-uniphier/boot-mode/boot-mode.c index b08cd6c..48e478c 100644 --- a/arch/arm/mach-uniphier/boot-mode/boot-mode.c +++ b/arch/arm/mach-uniphier/boot-mode/boot-mode.c @@ -39,6 +39,10 @@ u32 spl_boot_device_raw(void) case SOC_UNIPHIER_LD6B: return uniphier_pxs2_boot_device(); #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + return uniphier_ld20_boot_device(); +#endif default: return BOOT_DEVICE_NONE; } diff --git a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c index bccab62..fa97dc5 100644 --- a/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c +++ b/arch/arm/mach-uniphier/boot-mode/cmd_pinmon.c @@ -39,6 +39,11 @@ static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) uniphier_pxs2_boot_mode_show(); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + uniphier_ld20_boot_mode_show(); + break; +#endif default: break; } diff --git a/arch/arm/mach-uniphier/cpu_info.c b/arch/arm/mach-uniphier/cpu_info.c index aae8d1f..f9646c0 100644 --- a/arch/arm/mach-uniphier/cpu_info.c +++ b/arch/arm/mach-uniphier/cpu_info.c @@ -48,7 +48,7 @@ int print_cpuinfo(void) puts("PH1-LD11 ()"); break; case 0x32: - puts("PH1-LD20 ()"); + puts("PH1-LD20 (SC1401AJ1)"); break; default: printf("Unknown Processor ID (0x%x)\n", revision); diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile index 615ba2c..41aa53b 100644 --- a/arch/arm/mach-uniphier/dram/Makefile +++ b/arch/arm/mach-uniphier/dram/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += umc-sld8.o \ ddrphy-training.o ddrphy-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += umc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += umc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += umc-ld20.o
else
diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c new file mode 100644 index 0000000..dd6aca1 --- /dev/null +++ b/arch/arm/mach-uniphier/dram/umc-ld20.c @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" + +int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) +{ + return 0; +} diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile index 59058cd..9242b41 100644 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ b/arch/arm/mach-uniphier/early-clk/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c new file mode 100644 index 0000000..37adb37 --- /dev/null +++ b/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/io.h> + +#include "../init.h" +#include "../sc64-regs.h" + +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd) +{ + u32 tmp; + + /* deassert reset */ + tmp = readl(SC_RSTCTRL7); + tmp |= SC_RSTCTRL7_UMCSB | SC_RSTCTRL7_UMCA2 | SC_RSTCTRL7_UMCA1 | + SC_RSTCTRL7_UMCA0 | SC_RSTCTRL7_UMC32 | SC_RSTCTRL7_UMC31 | + SC_RSTCTRL7_UMC30; + writel(tmp, SC_RSTCTRL7); + + /* provide clocks */ + tmp = readl(SC_CLKCTRL7); + tmp |= SC_CLKCTRL7_UMCSB | SC_CLKCTRL7_UMC32 | SC_CLKCTRL7_UMC31 | + SC_CLKCTRL7_UMC30; + writel(tmp, SC_CLKCTRL7); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 3abf4aa..f46bfb0 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -32,6 +32,7 @@ int uniphier_pro4_init(const struct uniphier_board_data *bd); int uniphier_sld8_init(const struct uniphier_board_data *bd); int uniphier_pro5_init(const struct uniphier_board_data *bd); int uniphier_pxs2_init(const struct uniphier_board_data *bd); +int uniphier_ld20_init(const struct uniphier_board_data *bd);
#if defined(CONFIG_MICRO_SUPPORT_CARD) int uniphier_sbc_init_admulti(const struct uniphier_board_data *bd); @@ -86,6 +87,7 @@ int uniphier_ld4_enable_dpll_ssc(const struct uniphier_board_data *bd); int uniphier_ld4_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pro5_early_clk_init(const struct uniphier_board_data *bd); int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); +int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);
int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd);
@@ -93,6 +95,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); +int uniphier_ld20_umc_init(const struct uniphier_board_data *bd);
void uniphier_sld3_pin_init(void); void uniphier_ld4_pin_init(void); diff --git a/arch/arm/mach-uniphier/init/Makefile b/arch/arm/mach-uniphier/init/Makefile index 34b15e3..b58e6c8 100644 --- a/arch/arm/mach-uniphier/init/Makefile +++ b/arch/arm/mach-uniphier/init/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += init-sld8.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += init-pro5.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += init-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += init-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += init-ld20.o diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c new file mode 100644 index 0000000..87cca7e --- /dev/null +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +#include "../init.h" +#include "../micro-support-card.h" + +int uniphier_ld20_init(const struct uniphier_board_data *bd) +{ + uniphier_sbc_init_savepin(bd); + + support_card_reset(); + + support_card_init(); + + led_puts("L0"); + + memconf_init(bd); + uniphier_pxs2_memconf_init(bd); + + led_puts("L1"); + + uniphier_ld20_early_clk_init(bd); + + led_puts("L2"); + + led_puts("L3"); + +#ifdef CONFIG_SPL_SERIAL_SUPPORT + preloader_console_init(); +#endif + + led_puts("L4"); + + { + int res; + + res = uniphier_ld20_umc_init(bd); + if (res < 0) { + while (1) + ; + } + } + + led_puts("L5"); + + led_puts("L6"); + + return 0; +} diff --git a/arch/arm/mach-uniphier/init/init.c b/arch/arm/mach-uniphier/init/init.c index c56c44c..15a53ce 100644 --- a/arch/arm/mach-uniphier/init/init.c +++ b/arch/arm/mach-uniphier/init/init.c @@ -55,6 +55,11 @@ void spl_board_init(void) uniphier_pxs2_init(param); break; #endif +#if defined(CONFIG_ARCH_UNIPHIER_LD20) + case SOC_UNIPHIER_LD20: + uniphier_ld20_init(param); + break; +#endif default: break; } diff --git a/arch/arm/mach-uniphier/memconf/Makefile b/arch/arm/mach-uniphier/memconf/Makefile index 78bb677..6ed1419 100644 --- a/arch/arm/mach-uniphier/memconf/Makefile +++ b/arch/arm/mach-uniphier/memconf/Makefile @@ -6,3 +6,4 @@ obj-y += memconf.o obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += memconf-sld3.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += memconf-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += memconf-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += memconf-pxs2.o diff --git a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c index bf14d0d..e98eb48 100644 --- a/arch/arm/mach-uniphier/memconf/memconf-pxs2.c +++ b/arch/arm/mach-uniphier/memconf/memconf-pxs2.c @@ -49,6 +49,9 @@ int uniphier_pxs2_memconf_init(const struct uniphier_board_data *bd) case SZ_512M: tmp |= SG_MEMCONF_CH2_SZ_512M; break; + case SZ_1G: + tmp |= SG_MEMCONF_CH2_SZ_1G; + break; default: pr_err("error: unsupported DRAM Ch2 size\n"); return -EINVAL; diff --git a/arch/arm/mach-uniphier/sbc/Makefile b/arch/arm/mach-uniphier/sbc/Makefile index e515af9..3c1e92a 100644 --- a/arch/arm/mach-uniphier/sbc/Makefile +++ b/arch/arm/mach-uniphier/sbc/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += sbc-savepin.o sbc-ld4.o obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += sbc-savepin.o obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += sbc-savepin.o sbc-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += sbc-savepin.o sbc-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += sbc-savepin.o diff --git a/arch/arm/mach-uniphier/sg-regs.h b/arch/arm/mach-uniphier/sg-regs.h index 2cdc2db..ee8fac3 100644 --- a/arch/arm/mach-uniphier/sg-regs.h +++ b/arch/arm/mach-uniphier/sg-regs.h @@ -50,10 +50,11 @@ #define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) | (0x02 << 16)) #define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) | (0x03 << 16)) #define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) | (0x00 << 16)) +#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) | (0x01 << 16)) #define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24) #define SG_MEMCONF_CH2_NUM_1 (0x1 << 24) #define SG_MEMCONF_CH2_NUM_2 (0x0 << 24) -/* PH1-LD6b, ProXstream2 only */ +/* PH1-LD6b, ProXstream2, PH1-LD20 only */ #define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
#define SG_MEMCONF_SPARSEMEM (0x1 << 4) diff --git a/configs/uniphier_ld20_defconfig b/configs/uniphier_ld20_defconfig new file mode 100644 index 0000000..3a5bf02 --- /dev/null +++ b/configs/uniphier_ld20_defconfig @@ -0,0 +1,28 @@ +CONFIG_ARM=y +CONFIG_ARCH_UNIPHIER=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_UNIPHIER_LD20=y +CONFIG_MICRO_SUPPORT_CARD=y +CONFIG_SYS_TEXT_BASE=0x84000000 +CONFIG_DEFAULT_DEVICE_TREE="uniphier-ph1-ld20-ref" +CONFIG_HUSH_PARSER=y +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_ENV_EXISTS is not set +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +# CONFIG_CMD_MISC is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_GPIO_UNIPHIER=y +CONFIG_MMC_UNIPHIER=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_UNIPHIER_SERIAL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 963f55b..635d073 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -71,8 +71,7 @@ /* serial console configuration */ #define CONFIG_BAUDRATE 115200
- -#if !defined(CONFIG_SPL_BUILD) +#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_ARM64) #define CONFIG_USE_ARCH_MEMSET #define CONFIG_USE_ARCH_MEMCPY #endif @@ -99,8 +98,16 @@ #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SYS_MMC_ENV_PART 1
+#ifdef CONFIG_ARM64 +#define COUNTER_FREQUENCY 50000000 +#define CONFIG_GICV3 +#define GICD_BASE 0x5fe00000 +#define GICR_BASE 0x5fe80000 +#else /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 +#endif +
/* * By default, ARP timeout is 5 sec. @@ -184,21 +191,30 @@ "bootm $fit_addr_r\0" \ "__nfsboot=run tftpboot\0" #else +#ifdef CONFIG_ARM64 +#define CONFIG_CMD_BOOTI +#define CONFIG_BOOTFILE "Image" +#define LINUXBOOT_CMD "booti" +#define KERNEL_ADDR_R "kernel_addr_r=0x80080000\0" +#else #define CONFIG_CMD_BOOTZ #define CONFIG_BOOTFILE "zImage" +#define LINUXBOOT_CMD "bootz" +#define KERNEL_ADDR_R "kernel_addr_r=0x80208000\0" +#endif #define LINUXBOOT_ENV_SETTINGS \ "fdt_addr=0x00100000\0" \ "fdt_addr_r=0x84100000\0" \ "fdt_size=0x00008000\0" \ "kernel_addr=0x00200000\0" \ - "kernel_addr_r=0x80208000\0" \ + KERNEL_ADDR_R \ "kernel_size=0x00800000\0" \ "ramdisk_addr=0x00a00000\0" \ "ramdisk_addr_r=0x84a00000\0" \ "ramdisk_size=0x00600000\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 &&" \ - "bootz $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ + LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ "norboot=setexpr kernel_addr $nor_base + $kernel_addr &&" \ "cp.b $kernel_addr $kernel_addr_r $kernel_size &&" \ "setexpr ramdisk_addr_r $nor_base + $ramdisk_addr &&" \ @@ -246,14 +262,21 @@ #define CONFIG_SYS_SDRAM_BASE 0x80000000 #define CONFIG_NR_DRAM_BANKS 2
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || defined(CONFIG_ARCH_UNIPHIER_LD4) || \ +#if defined(CONFIG_ARM64) +#define CONFIG_SPL_TEXT_BASE 0x30000000 +#elif defined(CONFIG_ARCH_UNIPHIER_SLD3) || \ + defined(CONFIG_ARCH_UNIPHIER_LD4) || \ defined(CONFIG_ARCH_UNIPHIER_SLD8) #define CONFIG_SPL_TEXT_BASE 0x00040000 #else #define CONFIG_SPL_TEXT_BASE 0x00100000 #endif
+#if defined(CONFIG_ARCH_UNIPHIER_LD20) +#define CONFIG_SPL_STACK (0x3001c000) +#else #define CONFIG_SPL_STACK (0x00100000) +#endif #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE)
#define CONFIG_PANIC_HANG @@ -261,8 +284,10 @@ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_NOR_SUPPORT +#ifndef CONFIG_ARM64 #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_MMC_SUPPORT +#endif
#define CONFIG_SPL_LIBCOMMON_SUPPORT /* for mem_malloc_init */ #define CONFIG_SPL_LIBGENERIC_SUPPORT @@ -278,5 +303,7 @@ #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_MAX_FOOTPRINT 0x10000 #define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x30016000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000
#endif /* __CONFIG_UNIPHIER_COMMON_H__ */