T2080 v1.0 has this errata while v1.1 has fixed this errata by hardware, add a new function to check the SVR_SOC_VER, SVR_MAJ and SVR_MIN first, if the cpu is T2080 and version is not v1.0, doesn't run the a007212 errata_workaround.
Signed-off-by: Zhao Qiang B45475@freescale.com --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 2 ++ arch/powerpc/cpu/mpc85xx/speed.c | 3 ++- arch/powerpc/include/asm/fsl_errata.h | 14 ++++++++++++++ 4 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 741eb63..a50bb08 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -121,7 +121,7 @@ static void check_erratum_a007212(void) { u32 __iomem *plldgdcr = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
- if (in_be32(plldgdcr) & 0x1fe) { + if (!not_has_erratum_a007212() && in_be32(plldgdcr) & 0x1fe) { /* check if PLL ratio is set by workaround */ puts("Work-around for Erratum A007212 enabled\n"); } diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 78316a6..6219619 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -345,6 +345,8 @@ void fsl_erratum_a007212_workaround(void) u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68); #endif #endif + if (not_has_erratum_a007212()) + return; /* * Even this workaround applies to selected version of SoCs, it is * safe to apply to all versions, with the limitation of odd ratios. diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 3236f6a..904d19d 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -13,6 +13,7 @@ #include <common.h> #include <ppc_asm.tmpl> #include <linux/compiler.h> +#include <asm/fsl_errata.h> #include <asm/processor.h> #include <asm/io.h>
@@ -113,7 +114,7 @@ void get_sys_info(sys_info_t *sys_info) FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 - if (mem_pll_rat == 0) { + if (!not_has_erratum_a007212() && mem_pll_rat == 0) { mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) & FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK; diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h index a977544..8f7777d 100644 --- a/arch/powerpc/include/asm/fsl_errata.h +++ b/arch/powerpc/include/asm/fsl_errata.h @@ -96,3 +96,17 @@ static inline bool not_has_erratum_a007186(void) return false; } #endif + +#ifdef CONFIG_SYS_FSL_ERRATUM_A007212 +static inline bool not_has_erratum_a007212(void) +{ + u32 svr = get_svr(); + u32 soc = SVR_SOC_VER(svr); + + if (((soc == SVR_T2080) && (SVR_MAJ(svr) > 1)) || + ((soc == SVR_T2080) && (SVR_MAJ(svr) == 1) && (SVR_MIN(svr) > 0))) + return true; + + return false; +} +#endif