When boot from SRIO, slave's core can be in holdoff after powered on for some specific requirements. Master can release the slave's core at the right time by SRIO interface.
Master needs to: 1. Set outbound SRIO windows in order to configure slave's registers for the core's releasing. 2. Check the SRIO port status when release slave core, if no errors, will implement the process of the slave core's releasing. Slave needs to: 1. Set all the cores in holdoff by RCW. 2. Be powered on before master's boot.
Signed-off-by: Liu Gang Gang.Liu@freescale.com Signed-off-by: Shaohui Xie Shaohui.Xie@freescale.com --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 3 + arch/powerpc/cpu/mpc8xxx/srio.c | 114 +++++++++++++++++++++++++++++++++++ arch/powerpc/include/asm/fsl_srio.h | 3 + include/configs/corenet_ds.h | 4 + 4 files changed, 124 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 42d6475..9284e443 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -444,6 +444,9 @@ skip_l2: srio_init(); #ifdef CONFIG_SRIOBOOT_MASTER srio_boot_master(); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF + srio_boot_master_release_slave(); +#endif #endif #endif
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c899480..66ecf0b 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -23,6 +23,11 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_srio.h>
+#define RIO_LCSBA1CSR_OFFSET 0x5c +#define RIO_MAINT_WIN_SIZE 0x1000000 /* 16M */ +#define RIO_RW_WIN_SIZE 0x100000 /* 1M */ +#define RIO_LCSBA1CSR 0x60000000 + #if defined(CONFIG_FSL_CORENET) #define _DEVDISR_SRIO1 FSL_CORENET_DEVDISR_SRIO1 #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 @@ -153,4 +158,113 @@ void srio_boot_master(void) 0x80f55000 | atmu_size_mask(CONFIG_SRIOBOOT_SLAVE_ENV_SIZE)); } + +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +void srio_boot_master_release_slave(void) +{ + ccsr_rio_t *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + u32 escsr; + + printf("SRIOBOOT - MASTER: " + "Check the port status and release slave core ...\n"); + + escsr = in_be32((u32)&srio->pescsr + + CONFIG_SRIOBOOT_MASTER_PORT * 0x20); + if (escsr & 0x2) { + if (escsr & 0x10100) { + printf("SRIOBOOT - MASTER: Port [ %d ] is error.\n", + CONFIG_SRIOBOOT_MASTER_PORT); + } else { + printf("SRIOBOOT - MASTER: " + "Port [ %d ] is ready, now release slave's core ...\n", + CONFIG_SRIOBOOT_MASTER_PORT); + /* + * configure outbound window + * with maintenance attribute to set slave's LCSBA1CSR + */ + out_be32((u32)&srio->rowtar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0); + out_be32((u32)&srio->rowtear1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((u32)&srio->rowbar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SYS_SRIO2_MEM_PHYS >> 12); + else + out_be32((u32)&srio->rowbar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + CONFIG_SYS_SRIO1_MEM_PHYS >> 12); + out_be32((u32)&srio->rowar1 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80077000 + | atmu_size_mask(RIO_MAINT_WIN_SIZE)); + + /* + * configure outbound window + * with R/W attribute to set slave's BRR + */ + out_be32((u32)&srio->rowtar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + RIO_LCSBA1CSR >> 9); + out_be32((u32)&srio->rowtear2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, 0); + if (CONFIG_SRIOBOOT_MASTER_PORT) + out_be32((u32)&srio->rowbar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + (CONFIG_SYS_SRIO2_MEM_PHYS + + RIO_MAINT_WIN_SIZE) >> 12); + else + out_be32((u32)&srio->rowbar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + (CONFIG_SYS_SRIO1_MEM_PHYS + + RIO_MAINT_WIN_SIZE) >> 12); + out_be32((u32)&srio->rowar2 + + CONFIG_SRIOBOOT_MASTER_PORT * 0x200, + 0x80045000 + | atmu_size_mask(RIO_RW_WIN_SIZE)); + + /* + * Set the LCSBA1CSR register in slave + * by the maint-outbound window + */ + if (CONFIG_SRIOBOOT_MASTER_PORT) { + out_be32(CONFIG_SYS_SRIO2_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET, + RIO_LCSBA1CSR); + while (in_be32(CONFIG_SYS_SRIO2_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET) + != RIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32(CONFIG_SYS_SRIO2_MEM_VIRT + + RIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } else { + out_be32(CONFIG_SYS_SRIO1_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET, RIO_LCSBA1CSR); + while (in_be32(CONFIG_SYS_SRIO1_MEM_VIRT + + RIO_LCSBA1CSR_OFFSET) + != RIO_LCSBA1CSR) + ; + /* + * And then set the BRR register + * to release slave core + */ + out_be32(CONFIG_SYS_SRIO1_MEM_VIRT + + RIO_MAINT_WIN_SIZE + + CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET, + CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK); + } + printf("SRIOBOOT - MASTER: " + "Release slave successfully! Now the slave should start up!\n"); + } + } else + printf("SRIOBOOT - MASTER: Port [ %d ] is not ready.\n", + CONFIG_SRIOBOOT_MASTER_PORT); +} +#endif #endif diff --git a/arch/powerpc/include/asm/fsl_srio.h b/arch/powerpc/include/asm/fsl_srio.h index e4cd9b6..a905a26 100644 --- a/arch/powerpc/include/asm/fsl_srio.h +++ b/arch/powerpc/include/asm/fsl_srio.h @@ -57,5 +57,8 @@ enum atmu_size { extern void srio_init(void); #ifdef CONFIG_SRIOBOOT_MASTER extern void srio_boot_master(void); +#ifdef CONFIG_SRIOBOOT_SLAVE_HOLDOFF +extern void srio_boot_master_release_slave(void); +#endif #endif #endif diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index f974630..f34dffd 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -419,6 +419,10 @@ #define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull #define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +/* slave core release by master*/ +#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF +#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ #endif
/*