
On Thu, Apr 3, 2014 at 5:22 PM, Tom Rini trini@ti.com wrote:
From: "Poddar, Sourav" sourav.poddar@ti.com
Bulk erase is not happening properly on dra7 due to erase timing constraints, add a delay so that erase timing constraints are properly met.
Signed-off-by: Sourav Poddar sourav.poddar@ti.com Tested-by: Yebio Mesfin ymesfin@ti.com
drivers/spi/ti_qspi.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index dfa5d0c..c5d2245 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -314,6 +314,9 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, qslave->cmd |= QSPI_RD_SNGL; debug("rx cmd %08x dc %08x\n", qslave->cmd, qslave->dc);
#ifdef CONFIG_DRA7XX
udelay(500);
#endif writel(qslave->cmd, &qslave->base->cmd); status = readl(&qslave->base->status); timeout = QSPI_TIMEOUT;
Can't we fix this? discussed the same in previous version thread as well.
thanks!