Re: [U-Boot] [PATCH v3 1/2] mx6sabresd: Make SPL DDR configuration to match the DCD table

Any help?

On Wed, Mar 29, 2017 at 8:45 PM, Jagan Teki jagannadh.teki@gmail.com wrote:

Hi Fabio,

On Mon, Sep 26, 2016 at 5:44 PM, Fabio Estevam festevam@gmail.com wrote:

...

From: Fabio Estevam fabio.estevam@nxp.com

When using SPL on i.mx6 we frequently notice some DDR initialization mismatches between the SPL code and the non-SPL code.

This causes stability issues like the ones reported at 7dbda25ecd6d7c ("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also: http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .

As the non-SPL code have been tested for long time and proves to be reliable, let's configure the DDR in the exact same way as the non-SPL case.

The idea is simple: just use the DCD table and write directly to the DDR registers.

Retrieved the DCD tables from: board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg and board/freescale/mx6sabresd/mx6qp.cfg (NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)

This method makes it easier for people converting from non-SPL to SPL code.

Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.

Signed-off-by: Fabio Estevam fabio.estevam@nxp.com

Changes since v1:

• Use the correct mx6qp dcd table
• Create ddr_init() to write the DCD values
• Specify where the DCD tables come from

board/freescale/mx6sabresd/mx6sabresd.c | 351 ++++++++++++++++++-------------- 1 file changed, 197 insertions(+), 154 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index f836ecb..3c36395 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -682,125 +682,6 @@ int checkboard(void) #include <spl.h> #include <libfdt.h>

-const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {

•   .dram_sdclk_0 =  0x00020030,
  

•   .dram_sdclk_1 =  0x00020030,
  

•   .dram_cas =  0x00020030,
  

•   .dram_ras =  0x00020030,
  

•   .dram_reset =  0x00020030,
  

•   .dram_sdcke0 =  0x00003000,
  

•   .dram_sdcke1 =  0x00003000,
  

•   .dram_sdba2 =  0x00000000,
  

•   .dram_sdodt0 =  0x00003030,
  

•   .dram_sdodt1 =  0x00003030,
  

•   .dram_sdqs0 =  0x00000030,
  

•   .dram_sdqs1 =  0x00000030,
  

•   .dram_sdqs2 =  0x00000030,
  

•   .dram_sdqs3 =  0x00000030,
  

•   .dram_sdqs4 =  0x00000030,
  

•   .dram_sdqs5 =  0x00000030,
  

•   .dram_sdqs6 =  0x00000030,
  

•   .dram_sdqs7 =  0x00000030,
  

•   .dram_dqm0 =  0x00020030,
  

•   .dram_dqm1 =  0x00020030,
  

•   .dram_dqm2 =  0x00020030,
  

•   .dram_dqm3 =  0x00020030,
  

•   .dram_dqm4 =  0x00020030,
  

•   .dram_dqm5 =  0x00020030,
  

•   .dram_dqm6 =  0x00020030,
  

•   .dram_dqm7 =  0x00020030,
  

-};

-const struct mx6dq_iomux_ddr_regs mx6dqp_ddr_ioregs = {

•   .dram_sdclk_0 =  0x00000030,
  

•   .dram_sdclk_1 =  0x00000030,
  

•   .dram_cas =  0x00000030,
  

•   .dram_ras =  0x00000030,
  

•   .dram_reset =  0x00000030,
  

•   .dram_sdcke0 =  0x00003000,
  

•   .dram_sdcke1 =  0x00003000,
  

•   .dram_sdba2 =  0x00000000,
  

•   .dram_sdodt0 =  0x00003030,
  

•   .dram_sdodt1 =  0x00003030,
  

•   .dram_sdqs0 =  0x00000030,
  

•   .dram_sdqs1 =  0x00000030,
  

•   .dram_sdqs2 =  0x00000030,
  

•   .dram_sdqs3 =  0x00000030,
  

•   .dram_sdqs4 =  0x00000030,
  

•   .dram_sdqs5 =  0x00000030,
  

•   .dram_sdqs6 =  0x00000030,
  

•   .dram_sdqs7 =  0x00000030,
  

•   .dram_dqm0 =  0x00000030,
  

•   .dram_dqm1 =  0x00000030,
  

•   .dram_dqm2 =  0x00000030,
  

•   .dram_dqm3 =  0x00000030,
  

•   .dram_dqm4 =  0x00000030,
  

•   .dram_dqm5 =  0x00000030,
  

•   .dram_dqm6 =  0x00000030,
  

•   .dram_dqm7 =  0x00000030,
  

-};

-const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {

•   .grp_ddr_type =  0x000C0000,
  

•   .grp_ddrmode_ctl =  0x00020000,
  

•   .grp_ddrpke =  0x00000000,
  

•   .grp_addds =  0x00000030,
  

•   .grp_ctlds =  0x00000030,
  

•   .grp_ddrmode =  0x00020000,
  

•   .grp_b0ds =  0x00000030,
  

•   .grp_b1ds =  0x00000030,
  

•   .grp_b2ds =  0x00000030,
  

•   .grp_b3ds =  0x00000030,
  

•   .grp_b4ds =  0x00000030,
  

•   .grp_b5ds =  0x00000030,
  

•   .grp_b6ds =  0x00000030,
  

•   .grp_b7ds =  0x00000030,
  

-};

-const struct mx6_mmdc_calibration mx6_mmcd_calib = {

•   .p0_mpwldectrl0 =  0x001F001F,
  

•   .p0_mpwldectrl1 =  0x001F001F,
  

•   .p1_mpwldectrl0 =  0x00440044,
  

•   .p1_mpwldectrl1 =  0x00440044,
  

•   .p0_mpdgctrl0 =  0x434B0350,
  

•   .p0_mpdgctrl1 =  0x034C0359,
  

•   .p1_mpdgctrl0 =  0x434B0350,
  

•   .p1_mpdgctrl1 =  0x03650348,
  

•   .p0_mprddlctl =  0x4436383B,
  

•   .p1_mprddlctl =  0x39393341,
  

•   .p0_mpwrdlctl =  0x35373933,
  

•   .p1_mpwrdlctl =  0x48254A36,
  

-};

-const struct mx6_mmdc_calibration mx6dqp_mmcd_calib = {

•   .p0_mpwldectrl0 =  0x001B001E,
  

•   .p0_mpwldectrl1 =  0x002E0029,
  

•   .p1_mpwldectrl0 =  0x001B002A,
  

•   .p1_mpwldectrl1 =  0x0019002C,
  

•   .p0_mpdgctrl0 =  0x43240334,
  

•   .p0_mpdgctrl1 =  0x0324031A,
  

•   .p1_mpdgctrl0 =  0x43340344,
  

•   .p1_mpdgctrl1 =  0x03280276,
  

•   .p0_mprddlctl =  0x44383A3E,
  

•   .p1_mprddlctl =  0x3C3C3846,
  

•   .p0_mpwrdlctl =  0x2E303230,
  

•   .p1_mpwrdlctl =  0x38283E34,
  

-};

-/* MT41K128M16JT-125 */ -static struct mx6_ddr3_cfg mem_ddr = {

•   .mem_speed = 1600,
  

•   .density = 2,
  

•   .width = 16,
  

•   .banks = 8,
  

•   .rowaddr = 14,
  

•   .coladdr = 10,
  

•   .pagesz = 2,
  

•   .trcd = 1375,
  

•   .trcmin = 4875,
  

•   .trasmin = 3500,
  

-};

static void ccgr_init(void) { struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -831,44 +712,209 @@ static void gpr_init(void) } }

-/*

• • This section requires the differentiation between iMX6 Sabre boards, but
• • for now, it will configure only for the mx6q variant.
• */

-static void spl_dram_init(void) +static int mx6q_dcd_table[] = {

•   0x020e0798, 0x000C0000,
  

•   0x020e0758, 0x00000000,
  

•   0x020e0588, 0x00000030,
  

•   0x020e0594, 0x00000030,
  

•   0x020e056c, 0x00000030,
  

•   0x020e0578, 0x00000030,
  

•   0x020e074c, 0x00000030,
  

•   0x020e057c, 0x00000030,
  

•   0x020e058c, 0x00000000,
  

•   0x020e059c, 0x00000030,
  

•   0x020e05a0, 0x00000030,
  

•   0x020e078c, 0x00000030,
  

•   0x020e0750, 0x00020000,
  

•   0x020e05a8, 0x00000030,
  

•   0x020e05b0, 0x00000030,
  

•   0x020e0524, 0x00000030,
  

•   0x020e051c, 0x00000030,
  

•   0x020e0518, 0x00000030,
  

•   0x020e050c, 0x00000030,
  

•   0x020e05b8, 0x00000030,
  

•   0x020e05c0, 0x00000030,
  

•   0x020e0774, 0x00020000,
  

•   0x020e0784, 0x00000030,
  

•   0x020e0788, 0x00000030,
  

•   0x020e0794, 0x00000030,
  

•   0x020e079c, 0x00000030,
  

•   0x020e07a0, 0x00000030,
  

•   0x020e07a4, 0x00000030,
  

•   0x020e07a8, 0x00000030,
  

•   0x020e0748, 0x00000030,
  

•   0x020e05ac, 0x00000030,
  

•   0x020e05b4, 0x00000030,
  

•   0x020e0528, 0x00000030,
  

•   0x020e0520, 0x00000030,
  

•   0x020e0514, 0x00000030,
  

•   0x020e0510, 0x00000030,
  

•   0x020e05bc, 0x00000030,
  

•   0x020e05c4, 0x00000030,
  

•   0x021b0800, 0xa1390003,
  

•   0x021b080c, 0x001F001F,
  

•   0x021b0810, 0x001F001F,
  

•   0x021b480c, 0x001F001F,
  

•   0x021b4810, 0x001F001F,
  

•   0x021b083c, 0x43270338,
  

•   0x021b0840, 0x03200314,
  

•   0x021b483c, 0x431A032F,
  

•   0x021b4840, 0x03200263,
  

•   0x021b0848, 0x4B434748,
  

•   0x021b4848, 0x4445404C,
  

•   0x021b0850, 0x38444542,
  

•   0x021b4850, 0x4935493A,
  

•   0x021b081c, 0x33333333,
  

•   0x021b0820, 0x33333333,
  

•   0x021b0824, 0x33333333,
  

•   0x021b0828, 0x33333333,
  

•   0x021b481c, 0x33333333,
  

•   0x021b4820, 0x33333333,
  

•   0x021b4824, 0x33333333,
  

•   0x021b4828, 0x33333333,
  

•   0x021b08b8, 0x00000800,
  

•   0x021b48b8, 0x00000800,
  

•   0x021b0004, 0x00020036,
  

•   0x021b0008, 0x09444040,
  

•   0x021b000c, 0x555A7975,
  

•   0x021b0010, 0xFF538F64,
  

•   0x021b0014, 0x01FF00DB,
  

•   0x021b0018, 0x00001740,
  

•   0x021b001c, 0x00008000,
  

•   0x021b002c, 0x000026d2,
  

•   0x021b0030, 0x005A1023,
  

•   0x021b0040, 0x00000027,
  

•   0x021b0000, 0x831A0000,
  

•   0x021b001c, 0x04088032,
  

•   0x021b001c, 0x00008033,
  

•   0x021b001c, 0x00048031,
  

•   0x021b001c, 0x09408030,
  

•   0x021b001c, 0x04008040,
  

•   0x021b0020, 0x00005800,
  

•   0x021b0818, 0x00011117,
  

•   0x021b4818, 0x00011117,
  

•   0x021b0004, 0x00025576,
  

•   0x021b0404, 0x00011006,
  

•   0x021b001c, 0x00000000,
  

+};

I believe, this is a random reg-pick from mx6q_4x_mt41j128.cfg. Do we need to follow any specific order to assign these dcd reg-init?

thanks!

Jagan Teki Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream Maintainer Hyderabad, India.