For the RK3368, we use a multi-stage boot-process consisting of the following: 1. TPL: initalises DRAM, returns to boot-ROM (which then loads the next stage and transfers control to it) 2. SPL: a full-features SPL stage including OF_CONTROL and FIT image loading, which fetches the ATF, DTB and full U-Boot and then transfers control to the ATF (using the BL31 parameter block to indicate the location of BL33/U-Boot) 3. ATF: sets up the secure world and exits to BL33 (i.e. a full U-Boot) in the normal world 4. full U-Boot
TPL/SPL and the full U-Boot are built from this tree and need to run from distinct text addresses and with distinct initial stack pointer addresses.
This commit sets up the configuration to run: - TPL from the SRAM at 0xff8c0000 (note that the first 0x1000 are reserved for use by the boot-ROM and contain the SP when the TPL is entered) - SPL from DRAM at 0x0 - U-Boot from DRAM at 0x200000
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Simon Glass sjg@chromium.org ---
Changes in v3: None Changes in v2: None
include/configs/rk3368_common.h | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index ddb7df0..e35f4c0 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -29,6 +29,17 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00280000
+#define CONFIG_SPL_TEXT_BASE 0x00000000 +#define CONFIG_SPL_MAX_SIZE 0x40000 +#define CONFIG_SPL_BSS_START_ADDR 0x400000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 + +#define CONFIG_TPL_LDSCRIPT \ + "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" +#define CONFIG_TPL_TEXT_BASE 0xff8c1000 +#define CONFIG_TPL_MAX_SIZE 0x7000 +#define CONFIG_TPL_STACK 0xff8cffff + #define CONFIG_BOUNCE_BUFFER
#ifndef CONFIG_SPL_BUILD