Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: 02 May 2020 22:15 To: Pragnesh Patel pragnesh.patel@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Atish Patra atish.patra@wdc.com; Palmer Dabbelt palmerdabbelt@google.com; Bin Meng bmeng.cn@gmail.com; Paul Walmsley paul.walmsley@sifive.com; Troy Benjegerdes troy.benjegerdes@sifive.com; Anup Patel anup.patel@wdc.com; Sagar Kadam sagar.kadam@sifive.com; Rick Chen rick@andestech.com; Lukasz Majewski lukma@denx.de; Anatolij Gustschin agust@denx.de; Simon Glass sjg@chromium.org Subject: Re: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ethernet clock initialization in SPL
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On Sat, May 2, 2020 at 10:05 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
Hi Jagan,
-----Original Message----- From: Jagan Teki jagan@amarulasolutions.com Sent: 02 May 2020 21:44 To: Pragnesh Patel pragnesh.patel@sifive.com Cc: U-Boot-Denx u-boot@lists.denx.de; Atish Patra atish.patra@wdc.com; Palmer Dabbelt palmerdabbelt@google.com;
Bin
Meng bmeng.cn@gmail.com; Paul Walmsley
Troy Benjegerdes troy.benjegerdes@sifive.com; Anup Patel anup.patel@wdc.com; Sagar Kadam sagar.kadam@sifive.com; Rick
Chen
rick@andestech.com; Lukasz Majewski lukma@denx.de; Anatolij Gustschin agust@denx.de; Simon Glass sjg@chromium.org Subject: Re: [PATCH v7 10/22] clk: sifive: fu540-prci: ddr and ethernet clock initialization in SPL
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On Sat, May 2, 2020 at 3:38 PM Pragnesh Patel pragnesh.patel@sifive.com wrote:
Add ddr clock release reset and ehternet clock initialization for SPL
Why ethernet still require for SPL?
I think we have already discussed this in v6. https://patchwork.ozlabs.org/project/uboot/patch/20200329170538.25449- 10-pragnesh.patel@sifive.com/
Understand, then make a separate patch for "Ethernet SPL" but not in this series.
I will make a separate patch in this series. This series is not just for SPL MMC boot but the real intention is to replace FSBL with U-Boot SPL so all FSBL functionality should be in one series.