Re: [U-Boot] [PATCH 4/4 V3] EXYNOS: Move files from board/samsung to arch/arm

Hi Minkyu Kang,

Thank you for comments. Please find the clarificatio below.

On Wed, Jul 3, 2013 at 5:40 PM, Minkyu Kang mk7.kang@samsung.com wrote:

On 02/07/13 22:12, Rajeshwari Shinde wrote:

...

This patch performs the following:

1. Convert the assembly code for memory and clock initialization to C code.
2. Move the memory and clock init codes from board/samsung to arch/arm
3. Creat a common lowlevel_init file across Exynos4 and Exynos5. Converted the common lowlevel_init from assembly to C-code
4. Made spl_boot.c and tzpc_init.c common for both exynos4 and exynos5.
5. Enable CONFIG_SKIP_LOWLEVEL_INIT as stack pointer initialisation is already done in _main.
6. exynos-uboot-spl.lds made common across SMDKV310, Origen and SMDK5250.

TEST: Tested SD-MMC boot on SMDK5250 and Origen. Tested USB and SPI boot on SMDK5250 Compile tested for SMDKV310.

Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com

Changes in V2: - Rebased on latest u-boot-samsung tree. - Incorporated review comments from Minkyu Kang. Changes in V3: - Optimised the mem_ctrl_init function for exynos4. - Removed magic numbers. arch/arm/cpu/armv7/exynos/Makefile | 17 +- .../arm/cpu/armv7/exynos}/clock_init.h | 0 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c | 94 +++++ .../arm/cpu/armv7/exynos/clock_init_exynos5.c | 47 +-- arch/arm/cpu/armv7/exynos/common_setup.h | 43 ++ .../arm/cpu/armv7/exynos}/dmc_common.c | 7 +- .../arm/cpu/armv7/exynos}/dmc_init_ddr3.c | 19 +- arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c | 212 ++++++++++ .../arm/cpu/armv7/exynos/exynos4_setup.h | 397 +++++++++---------- .../arm/cpu/armv7/exynos/exynos5_setup.h | 28 +- arch/arm/cpu/armv7/exynos/lowlevel_init.c | 73 ++++ .../arm/cpu/armv7/exynos}/spl_boot.c | 74 +++- arch/arm/include/asm/arch-exynos/cpu.h | 5 +- board/samsung/origen/Makefile | 11 +- board/samsung/origen/lowlevel_init.S | 357 ----------------- board/samsung/origen/mem_setup.S | 421 -------------------- board/samsung/origen/mmc_boot.c | 58 --- board/samsung/smdk5250/Makefile | 14 +- board/samsung/smdkv310/Makefile | 10 +- board/samsung/smdkv310/lowlevel_init.S | 414 ------------------- board/samsung/smdkv310/mem_setup.S | 365 ----------------- board/samsung/smdkv310/mmc_boot.c | 60 --- include/configs/exynos5250-dt.h | 8 +- include/configs/origen.h | 8 +- include/configs/smdkv310.h | 7 +- 25 files changed, 770 insertions(+), 1979 deletions(-) rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/clock_init.h (100%) create mode 100644 arch/arm/cpu/armv7/exynos/clock_init_exynos4.c rename board/samsung/smdk5250/clock_init.c => arch/arm/cpu/armv7/exynos/clock_init_exynos5.c (95%) create mode 100644 arch/arm/cpu/armv7/exynos/common_setup.h rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_common.c (97%) rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/dmc_init_ddr3.c (95%) create mode 100644 arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c rename board/samsung/origen/origen_setup.h => arch/arm/cpu/armv7/exynos/exynos4_setup.h (65%) rename board/samsung/smdk5250/setup.h => arch/arm/cpu/armv7/exynos/exynos5_setup.h (96%) create mode 100644 arch/arm/cpu/armv7/exynos/lowlevel_init.c rename {board/samsung/smdk5250 => arch/arm/cpu/armv7/exynos}/spl_boot.c (74%) delete mode 100644 board/samsung/origen/lowlevel_init.S delete mode 100644 board/samsung/origen/mem_setup.S delete mode 100644 board/samsung/origen/mmc_boot.c delete mode 100644 board/samsung/smdkv310/lowlevel_init.S delete mode 100644 board/samsung/smdkv310/mem_setup.S delete mode 100644 board/samsung/smdkv310/mmc_boot.c

diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index b2f9152..4661155 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,10 +22,19 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(SOC).o

-COBJS += clock.o power.o soc.o system.o pinmux.o tzpc.o

-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +COBJS-y += clock.o power.o soc.o system.o pinmux.o tzpc.o

+ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_EXYNOS5) += clock_init_exynos5.o +COBJS-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o +COBJS-$(CONFIG_EXYNOS4210)+= dmc_init_exynos4.o clock_init_exynos4.o +COBJS-y += spl_boot.o +COBJS-y += lowlevel_init.o +endif

+COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS))

all: $(obj).depend $(LIB)

diff --git a/board/samsung/smdk5250/clock_init.h b/arch/arm/cpu/armv7/exynos/clock_init.h similarity index 100% rename from board/samsung/smdk5250/clock_init.h rename to arch/arm/cpu/armv7/exynos/clock_init.h diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c new file mode 100644 index 0000000..bee0b5c --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos4.c @@ -0,0 +1,94 @@ +/*

• • Clock Initialization for board based on EXYNOS4210
• • Copyright (C) 2013 Samsung Electronics
• • Rajeshwari Shinde rajeshwari.s@samsung.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <config.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clk.h> +#include <asm/arch/clock.h> +#include "common_setup.h" +#include "exynos4_setup.h"

+/*

• • system_clock_init: Initialize core clock and bus clock.
• • void system_clock_init(void)
• */

+void system_clock_init(void) +{

• struct exynos4_clock *clk = (struct exynos4_clock *)EXYNOS4_CLOCK_BASE;
  

NAK.

Will correct this

...

• writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
  

• sdelay(0x10000);
  

• writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
  

• writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
  

• writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
  

• writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
  

• writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
  

• writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
  

• writel(CLK_SRC_PERIL0_VAL, &clk->src_peril0);
  

• writel(CLK_SRC_CAM_VAL, &clk->src_cam);
  

• writel(CLK_SRC_MFC_VAL, &clk->src_mfc);
  

• writel(CLK_SRC_G3D_VAL, &clk->src_g3d);
  

• writel(CLK_SRC_LCD0_VAL, &clk->src_lcd0);
  

• sdelay(0x10000);
  

• writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
  

• writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
  

• writel(CLK_DIV_DMC0_VAL, &clk->div_dmc0);
  

• writel(CLK_DIV_DMC1_VAL, &clk->div_dmc1);
  

• writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus);
  

• writel(CLK_DIV_RIGHTBUS_VAL, &clk->div_rightbus);
  

• writel(CLK_DIV_TOP_VAL, &clk->div_top);
  

• writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
  

• writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
  

• writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
  

• writel(CLK_DIV_PERIL0_VAL, &clk->div_peril0);
  

• writel(CLK_DIV_CAM_VAL, &clk->div_cam);
  

• writel(CLK_DIV_MFC_VAL, &clk->div_mfc);
  

• writel(CLK_DIV_G3D_VAL, &clk->div_g3d);
  

• writel(CLK_DIV_LCD0_VAL, &clk->div_lcd0);
  

• /* Set PLL locktime */
  

• writel(PLL_LOCKTIME, &clk->apll_lock);
  

• writel(PLL_LOCKTIME, &clk->mpll_lock);
  

• writel(PLL_LOCKTIME, &clk->epll_lock);
  

• writel(PLL_LOCKTIME, &clk->vpll_lock);
  

• writel(APLL_CON1_VAL, &clk->apll_con1);
  

• writel(APLL_CON0_VAL, &clk->apll_con0);
  

• writel(MPLL_CON1_VAL, &clk->mpll_con1);
  

• writel(MPLL_CON0_VAL, &clk->mpll_con0);
  

• writel(EPLL_CON1_VAL, &clk->epll_con1);
  

• writel(EPLL_CON0_VAL, &clk->epll_con0);
  

• writel(VPLL_CON1_VAL, &clk->vpll_con1);
  

• writel(VPLL_CON0_VAL, &clk->vpll_con0);
  

• sdelay(0x30000);
  

+}

...

diff --git a/board/samsung/smdk5250/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c similarity index 95% rename from board/samsung/smdk5250/dmc_init_ddr3.c rename to arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c index e050790..de54af8 100644 --- a/board/samsung/smdk5250/dmc_init_ddr3.c +++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c @@ -27,7 +27,8 @@ #include <asm/arch/clock.h> #include <asm/arch/cpu.h> #include <asm/arch/dmc.h> -#include "setup.h" +#include "common_setup.h" +#include "exynos5_setup.h" #include "clock_init.h"

#define RDLVL_COMPLETE_TIMEOUT 10000 @@ -40,7 +41,8 @@ static void reset_phy_ctrl(void) writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl); }

-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size) +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,

•                int reset)
  

{ unsigned int val; struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl; @@ -49,9 +51,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)

  phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
  phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;

NAK. Please use function instead.

Will correct this.

...

• dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
  

• dmc = (struct exynos5_dmc *)samsung_get_base_dmc0();
  
  

• reset_phy_ctrl();
  

• if (reset)
  

•         reset_phy_ctrl();
  
  /* Set Impedance Output Driver */
  val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
  

@@ -100,14 +103,14 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)

  /* Start DLL locking */
  writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),

•         &phy0_ctrl->phy_con12);
  

•        &phy0_ctrl->phy_con12);
  writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
  

•         &phy1_ctrl->phy_con12);
  

•        &phy1_ctrl->phy_con12);
  
  update_reset_dll(dmc, DDR_MODE_DDR3);
  
  writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
  

•         &dmc->concontrol);
  

•        &dmc->concontrol);
  
  /* Memory Channel Inteleaving Size */
  writel(mem->iv_size, &dmc->ivcontrol);
  

@@ -119,7 +122,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size)

  /* Precharge Configuration */
  writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,

•         &dmc->prechconfig);
  

•        &dmc->prechconfig);
  
  /* Power Down mode Configuration */
  writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
  

diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c new file mode 100644 index 0000000..636d84c --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/dmc_init_exynos4.c @@ -0,0 +1,212 @@ +/*

• • Memory setup for board based on EXYNOS4210
• • Copyright (C) 2013 Samsung Electronics
• • Rajeshwari Shinde rajeshwari.s@samsung.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <config.h> +#include <asm/arch/dmc.h> +#include "common_setup.h" +#include "exynos4_setup.h"

+struct mem_timings mem = {

• .direct_cmd_msr = {
  

•         DIRECT_CMD1, DIRECT_CMD2, DIRECT_CMD3, DIRECT_CMD4
  

• },
  

• .timingref = TIMINGREF_VAL,
  

• .timingrow = TIMINGROW_VAL,
  

• .timingdata = TIMINGDATA_VAL,
  

• .timingpower = TIMINGPOWER_VAL,
  

• .zqcontrol = ZQ_CONTROL_VAL,
  

• .control0 = CONTROL0_VAL,
  

• .control1 = CONTROL1_VAL,
  

• .control2 = CONTROL2_VAL,
  

• .concontrol = CONCONTROL_VAL,
  

• .prechconfig = PRECHCONFIG,
  

• .memcontrol = MEMCONTROL_VAL,
  

• .memconfig0 = MEMCONFIG0_VAL,
  

• .memconfig1 = MEMCONFIG1_VAL,
  

• .dll_resync = FORCE_DLL_RESYNC,
  

• .dll_on = DLL_CONTROL_ON,
  

+}; +static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) +{

• if (ctrl_no) {
  

•         writel((mem.control1 | (1 << mem.dll_resync)),
  

•                &dmc->phycontrol1);
  

•         writel((mem.control1 | (0 << mem.dll_resync)),
  

•                &dmc->phycontrol1);
  

• } else {
  

•         writel((mem.control0 | (0 << mem.dll_on)),
  

•                &dmc->phycontrol0);
  

•         writel((mem.control0 | (1 << mem.dll_on)),
  

•                &dmc->phycontrol0);
  

• }
  

+}

+static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) +{

• int i;
  

• unsigned long mask = 0;
  

• if (chip)
  

•         mask = DIRECT_CMD_CHIP1_SHIFT;
  

• for (i = 0; i < MEM_TIMINGS_MSR_COUNT; i++) {
  

•         writel(mem.direct_cmd_msr[i] | mask,
  

•                &dmc->directcmd);
  

• }
  

+}

+static void dmc_init(struct exynos4_dmc *dmc) +{

• /*
  

•  * DLL Parameter Setting:
  

•  * Termination: Enable R/W
  

•  * Phase Delay for DQS Cleaning: 180' Shift
  

•  */
  

• writel(mem.control1, &dmc->phycontrol1);
  

• /*
  

•  * ZQ Calibration
  

•  * Termination: Disable
  

•  * Auto Calibration Start: Enable
  

•  */
  

• writel(mem.zqcontrol, &dmc->phyzqcontrol);
  

• sdelay(0x100000);
  

• /*
  

•  * Update DLL Information:
  

•  * Force DLL Resyncronization
  

•  */
  

• phy_control_reset(1, dmc);
  

• phy_control_reset(0, dmc);
  

• /* Set DLL Parameters */
  

• writel(mem.control1, &dmc->phycontrol1);
  

• /* DLL Start */
  

• writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0);
  

• writel(mem.control2, &dmc->phycontrol2);
  

• /* Set Clock Ratio of Bus clock to Memory Clock */
  

• writel(mem.concontrol, &dmc->concontrol);
  

• /*
  

•  * Memor Burst length: 8
  

•  * Number of chips: 2
  

•  * Memory Bus width: 32 bit
  

•  * Memory Type: DDR3
  

•  * Additional Latancy for PLL: 1 Cycle
  

•  */
  

• writel(mem.memcontrol, &dmc->memcontrol);
  

• writel(mem.memconfig0, &dmc->memconfig0);
  

• writel(mem.memconfig1, &dmc->memconfig1);
  

• /* Config Precharge Policy */
  

• writel(mem.prechconfig, &dmc->prechconfig);
  

• /*
  

•  * TimingAref, TimingRow, TimingData, TimingPower Setting:
  

•  * Values as per Memory AC Parameters
  

•  */
  

• writel(mem.timingref, &dmc->timingref);
  

• writel(mem.timingrow, &dmc->timingrow);
  

• writel(mem.timingdata, &dmc->timingdata);
  

• writel(mem.timingpower, &dmc->timingpower);
  

• /* Chip0: NOP Command: Assert and Hold CKE to high level */
  

• writel(DIRECT_CMD_NOP, &dmc->directcmd);
  

• sdelay(0x100000);
  

• /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
  

• dmc_config_mrs(dmc, 0);
  

• sdelay(0x100000);
  

• /* Chip0: ZQINIT */
  

• writel(DIRECT_CMD_ZQ, &dmc->directcmd);
  

• sdelay(0x100000);
  

• writel((DIRECT_CMD_NOP | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
  

• sdelay(0x100000);
  

• /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */
  

• dmc_config_mrs(dmc, 1);
  

• sdelay(0x100000);
  

• /* Chip1: ZQINIT */
  

• writel((DIRECT_CMD_ZQ | DIRECT_CMD_CHIP1_SHIFT), &dmc->directcmd);
  

• sdelay(0x100000);
  

• phy_control_reset(1, dmc);
  

• sdelay(0x100000);
  

• /* turn on DREX0, DREX1 */
  

• writel((mem.concontrol | AREF_EN), &dmc->concontrol);
  

+}

+void mem_ctrl_init(int reset) +{

• struct exynos4_dmc *dmc;
  

• /*
  

•  * Async bridge configuration at CPU_core:
  

•  * 1: half_sync
  

•  * 0: full_sync
  

•  */
  

• writel(1, ASYNC_CONFIG);
  

+#ifdef CONFIG_ORIGEN

• /* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
  

• writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
  

•         APB_SFR_INTERLEAVE_CONF_OFFSET);
  

• /* Update MIU Configuration */
  

• writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +
  

•         APB_SFR_ARBRITATION_CONF_OFFSET);
  

+#else

• writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +
  

•         APB_SFR_INTERLEAVE_CONF_OFFSET);
  

• writel(INTERLEAVE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET);
  

• writel(INTERLEAVE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET);
  

• writel(INTERLEAVE_ADDR_MAP_EN, EXYNOS4_MIU_BASE +
  

•         ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
  

+#ifdef CONFIG_MIU_LINEAR

• writel(SLAVE0_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET);
  

• writel(SLAVE0_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET);
  

• writel(SLAVE1_SINGLE_ADDR_MAP_START_ADDR, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET);
  

• writel(SLAVE1_SINGLE_ADDR_MAP_END_ADDR, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET);
  

• writel(APB_SFR_SLV_ADDR_MAP_CONF_VAL, EXYNOS4_MIU_BASE +
  

•        ABP_SFR_SLV_ADDRMAP_CONF_OFFSET);
  

+#endif +#endif

• /* DREX0 */
  

• dmc = (struct exynos4_dmc *)samsung_get_base_dmc0();
  

• dmc_init(dmc);
  

• dmc = (struct exynos4_dmc *)samsung_get_base_dmc1();
  

• dmc_init(dmc);
  

+} diff --git a/board/samsung/origen/origen_setup.h b/arch/arm/cpu/armv7/exynos/exynos4_setup.h similarity index 65% rename from board/samsung/origen/origen_setup.h rename to arch/arm/cpu/armv7/exynos/exynos4_setup.h index 926a4cc..6d25058 100644 --- a/board/samsung/origen/origen_setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos4_setup.h @@ -1,5 +1,5 @@ /*

• • Machine Specific Values for ORIGEN board based on S5PV310

• • Machine Specific Values for EXYNOS4012 based board
  • Copyright (C) 2011 Samsung Electronics

@@ -29,98 +29,22 @@ #include <version.h> #include <asm/arch/cpu.h>

-/* Offsets of clock registers (sources and dividers) */ -#define CLK_SRC_CPU_OFFSET 0x14200 -#define CLK_DIV_CPU0_OFFSET 0x14500 -#define CLK_DIV_CPU1_OFFSET 0x14504

-#define CLK_SRC_DMC_OFFSET 0x10200 -#define CLK_DIV_DMC0_OFFSET 0x10500 -#define CLK_DIV_DMC1_OFFSET 0x10504

-#define CLK_SRC_TOP0_OFFSET 0xC210 -#define CLK_SRC_TOP1_OFFSET 0xC214 -#define CLK_DIV_TOP_OFFSET 0xC510

-#define CLK_SRC_LEFTBUS_OFFSET 0x4200 -#define CLK_DIV_LEFTBUS_OFFSET 0x4500

-#define CLK_SRC_RIGHTBUS_OFFSET 0x8200 -#define CLK_DIV_RIGHTBUS_OFFSET 0x8500

-#define CLK_SRC_FSYS_OFFSET 0xC240 -#define CLK_DIV_FSYS1_OFFSET 0xC544 -#define CLK_DIV_FSYS2_OFFSET 0xC548 -#define CLK_DIV_FSYS3_OFFSET 0xC54C

-#define CLK_SRC_CAM_OFFSET 0xC220 -#define CLK_SRC_TV_OFFSET 0xC224 -#define CLK_SRC_MFC_OFFSET 0xC228 -#define CLK_SRC_G3D_OFFSET 0xC22C -#define CLK_SRC_LCD0_OFFSET 0xC234 -#define CLK_SRC_PERIL0_OFFSET 0xC250

-#define CLK_DIV_CAM_OFFSET 0xC520 -#define CLK_DIV_TV_OFFSET 0xC524 -#define CLK_DIV_MFC_OFFSET 0xC528 -#define CLK_DIV_G3D_OFFSET 0xC52C -#define CLK_DIV_LCD0_OFFSET 0xC534 -#define CLK_DIV_PERIL0_OFFSET 0xC550

-#define CLK_SRC_LCD0_OFFSET 0xC234

-#define APLL_LOCK_OFFSET 0x14000 -#define MPLL_LOCK_OFFSET 0x14008 -#define APLL_CON0_OFFSET 0x14100 -#define APLL_CON1_OFFSET 0x14104 -#define MPLL_CON0_OFFSET 0x14108 -#define MPLL_CON1_OFFSET 0x1410C

-#define EPLL_LOCK_OFFSET 0xC010 -#define VPLL_LOCK_OFFSET 0xC020 -#define EPLL_CON0_OFFSET 0xC110 -#define EPLL_CON1_OFFSET 0xC114 -#define VPLL_CON0_OFFSET 0xC120 -#define VPLL_CON1_OFFSET 0xC124

-/* DMC: DRAM Controllor Register offsets */ -#define DMC_CONCONTROL 0x00 -#define DMC_MEMCONTROL 0x04 -#define DMC_MEMCONFIG0 0x08 -#define DMC_MEMCONFIG1 0x0C -#define DMC_DIRECTCMD 0x10 -#define DMC_PRECHCONFIG 0x14 -#define DMC_PHYCONTROL0 0x18 -#define DMC_PHYCONTROL1 0x1C -#define DMC_PHYCONTROL2 0x20 -#define DMC_TIMINGAREF 0x30 -#define DMC_TIMINGROW 0x34 -#define DMC_TIMINGDATA 0x38 -#define DMC_TIMINGPOWER 0x3C -#define DMC_PHYZQCONTROL 0x44 +#ifdef CONFIG_CLK_800_330_165 +#define DRAM_CLK_330 +#endif +#ifdef CONFIG_CLK_1000_200_200 +#define DRAM_CLK_200 +#endif +#ifdef CONFIG_CLK_1000_330_165 +#define DRAM_CLK_330 +#endif +#ifdef CONFIG_CLK_1000_400_200 +#define DRAM_CLK_400 +#endif

/* Bus Configuration Register Address */ #define ASYNC_CONFIG 0x10010350

-/* MIU Config Register Offsets*/ -#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 -#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00

-/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804

-/* GPIO Offsets for UART: GPIO Contol Register */ -#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00 -#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20

-/* UART Register offsets */ -#define ULCON_OFFSET 0x00 -#define UCON_OFFSET 0x04 -#define UFCON_OFFSET 0x08 -#define UBRDIV_OFFSET 0x28 -#define UFRACVAL_OFFSET 0x2C

/* CLK_SRC_CPU */ #define MUX_HPM_SEL_MOUTAPLL 0x0 #define MUX_HPM_SEL_SCLKMPLL 0x1 @@ -485,123 +409,186 @@ | (VPLL_MRR << 24) \ | (VPLL_MFR << 16) \ | (VPLL_K << 0)) -/*

• • UART GPIO_A0/GPIO_A1 Control Register Value
• • 0x2: UART Function
• */

-#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222 -#define EXYNOS4_GPIO_A1_CON_VAL 0x222222

-/* ULCON: UART Line Control Value 8N1 */ -#define WORD_LEN_5_BIT 0x00 -#define WORD_LEN_6_BIT 0x01 -#define WORD_LEN_7_BIT 0x02 -#define WORD_LEN_8_BIT 0x03

-#define STOP_BIT_1 0x00 -#define STOP_BIT_2 0x01

-#define NO_PARITY 0x00 -#define ODD_PARITY 0x4 -#define EVEN_PARITY 0x5 -#define FORCED_PARITY_CHECK_AS_1 0x6 -#define FORCED_PARITY_CHECK_AS_0 0x7

-#define INFRAMODE_NORMAL 0x00 -#define INFRAMODE_INFRARED 0x01

-#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \

•                         | (NO_PARITY << 3) \
  

•                         | (STOP_BIT_1 << 2) \
  

•                         | (WORD_LEN_8_BIT << 0))
  
  

-/*

• • UCON: UART Control Value
• • Tx_interrupt Type: Level
• • Rx_interrupt Type: Level
• • Rx Timeout Enabled: Yes
• • Rx-Error Atatus_Int Enable: Yes
• • Loop_Back: No
• • Break Signal: No
• • Transmit mode : Interrupt request/polling
• • Receive mode : Interrupt request/polling
• */

-#define TX_PULSE_INTERRUPT 0 -#define TX_LEVEL_INTERRUPT 1 -#define RX_PULSE_INTERRUPT 0 -#define RX_LEVEL_INTERRUPT 1

-#define RX_TIME_OUT ENABLE -#define RX_ERROR_STATE_INT_ENB ENABLE -#define LOOP_BACK DISABLE -#define BREAK_SIGNAL DISABLE

-#define TX_MODE_DISABLED 0X00 -#define TX_MODE_IRQ_OR_POLL 0X01 -#define TX_MODE_DMA 0X02

-#define RX_MODE_DISABLED 0X00 -#define RX_MODE_IRQ_OR_POLL 0X01 -#define RX_MODE_DMA 0X02

-#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \

•                         | (RX_LEVEL_INTERRUPT << 8) \
  

•                         | (RX_TIME_OUT << 7) \
  

•                         | (RX_ERROR_STATE_INT_ENB << 6) \
  

•                         | (LOOP_BACK << 5) \
  

•                         | (BREAK_SIGNAL << 4) \
  

•                         | (TX_MODE_IRQ_OR_POLL << 2) \
  

•                         | (RX_MODE_IRQ_OR_POLL << 0))
  

+/* DMC */ +#define DIRECT_CMD_NOP 0x07000000 +#define DIRECT_CMD_ZQ 0x0a000000 +#define DIRECT_CMD_CHIP1_SHIFT (1 << 20) +#define MEM_TIMINGS_MSR_COUNT 4 +#define CTRL_START (1 << 0) +#define CTRL_DLL_ON (1 << 1) +#define AREF_EN (1 << 5) +#define DRV_TYPE (1 << 6)

+struct mem_timings {

• unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];
  

• unsigned timingref;
  

• unsigned timingrow;
  

• unsigned timingdata;
  

• unsigned timingpower;
  

• unsigned zqcontrol;
  

• unsigned control0;
  

• unsigned control1;
  

• unsigned control2;
  

• unsigned concontrol;
  

• unsigned prechconfig;
  

• unsigned memcontrol;
  

• unsigned memconfig0;
  

• unsigned memconfig1;
  

• unsigned dll_resync;
  

• unsigned dll_on;
  

+};

+/* MIU */ +/* MIU Config Register Offsets*/ +#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 +#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00 +#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800 +#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808 +#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET 0x810 +#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET 0x818 +#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET 0x820 +#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET 0x828 +#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET 0x830

+#ifdef CONFIG_ORIGEN +/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */ +#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507 +#define APB_SFR_ARBRITATION_CONF_VAL 0x00000001 +#endif

-/*

• • UFCON: UART FIFO Control Value
• • Tx FIFO Trigger LEVEL: 2 Bytes (001)
• • Rx FIFO Trigger LEVEL: 2 Bytes (001)
• • Tx Fifo Reset: No
• • Rx Fifo Reset: No
• • FIFO Enable: Yes
• */

-#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00 -#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1 -#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2 -#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3 -#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4 -#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5 -#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6 -#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7

-#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0 -#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1 -#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2 -#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3 -#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4 -#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5 -#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6 -#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7

-#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES -#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES -#define TX_FIFO_RESET DISABLE -#define RX_FIFO_RESET DISABLE -#define FIFO_ENABLE ENABLE -#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \

•                                 | (RX_FIFO_TRIGGER_LEVEL << 4) \
  

•                                 | (TX_FIFO_RESET << 2) \
  

•                                 | (RX_FIFO_RESET << 1) \
  

•                                 | (FIFO_ENABLE << 0))
  

-/*

• • Baud Rate Division Value
• • 115200 BAUD:
• • UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1)
• • UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1)
• */

-#define UBRDIV_VAL 0x35 +#define INTERLEAVE_ADDR_MAP_START_ADDR 0x40000000 +#define INTERLEAVE_ADDR_MAP_END_ADDR 0xbfffffff +#define INTERLEAVE_ADDR_MAP_EN 0x00000001

-/*

• • Fractional Part of Baud Rate Divisor:
• • 115200 BAUD:
• • UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10)
• • UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10)
• */

-#define UFRACVAL_VAL 0x4 +#ifdef CONFIG_MIU_1BIT_INTERLEAVED +/* Interleave_bit0: 0xC*/ +#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c +#endif +#ifdef CONFIG_MIU_2BIT_INTERLEAVED +/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */ +#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c +#endif +#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR 0x40000000 +#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR 0x7fffffff +#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR 0x80000000 +#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR 0xbfffffff +/* Enable SME0 and SME1*/ +#define APB_SFR_SLV_ADDR_MAP_CONF_VAL 0x00000006

+#define FORCE_DLL_RESYNC 3 +#define DLL_CONTROL_ON 1

+#define DIRECT_CMD1 0x00020000 +#define DIRECT_CMD2 0x00030000 +#define DIRECT_CMD3 0x00010002 +#define DIRECT_CMD4 0x00000328

+#define CTRL_ZQ_MODE_NOTERM (0x1 << 0) +#define CTRL_ZQ_START (0x1 << 1) +#define CTRL_ZQ_DIV (0 << 4) +#define CTRL_ZQ_MODE_DDS (0x7 << 8) +#define CTRL_ZQ_MODE_TERM (0x2 << 11) +#define CTRL_ZQ_FORCE_IMPN (0x5 << 14) +#define CTRL_ZQ_FORCE_IMPP (0x6 << 17) +#define CTRL_DCC (0xE38 << 20) +#define ZQ_CONTROL_VAL (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\

•                         | CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\
  

•                         | CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\
  

•                         | CTRL_ZQ_FORCE_IMPP | CTRL_DCC)
  

+#define ASYNC (0 << 0) +#define CLK_RATIO (1 << 1) +#define DIV_PIPE (1 << 3) +#define AWR_ON (1 << 4) +#define AREF_DISABLE (0 << 5) +#define DRV_TYPE_DISABLE (0 << 6) +#define CHIP0_NOT_EMPTY (0 << 8) +#define CHIP1_NOT_EMPTY (0 << 9) +#define DQ_SWAP_DISABLE (0 << 10) +#define QOS_FAST_DISABLE (0 << 11) +#define RD_FETCH (0x3 << 12) +#define TIMEOUT_LEVEL0 (0xFFF << 16) +#define CONCONTROL_VAL (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\

•                         | AREF_DISABLE | DRV_TYPE_DISABLE\
  

•                         | CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\
  

•                         | DQ_SWAP_DISABLE | QOS_FAST_DISABLE\
  

•                         | RD_FETCH | TIMEOUT_LEVEL0)
  

+#define CLK_STOP_DISABLE (0 << 1) +#define DPWRDN_DISABLE (0 << 2) +#define DPWRDN_TYPE (0 << 3) +#define TP_DISABLE (0 << 4) +#define DSREF_DIABLE (0 << 5) +#define ADD_LAT_PALL (1 << 6) +#define MEM_TYPE_DDR3 (0x6 << 8) +#define MEM_WIDTH_32 (0x2 << 12) +#define NUM_CHIP_2 (1 << 16) +#define BL_8 (0x3 << 20) +#define MEMCONTROL_VAL (CLK_STOP_DISABLE | DPWRDN_DISABLE\

•                         | DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\
  

•                         | ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\
  

•                         | NUM_CHIP_2 | BL_8)
  

+#define CHIP_BANK_8 (0x3 << 0) +#define CHIP_ROW_14 (0x2 << 4) +#define CHIP_COL_10 (0x3 << 8) +#define CHIP_MAP_INTERLEAVED (1 << 12) +#define CHIP_MASK (0xe0 << 16) +#ifdef CONFIG_MIU_LINEAR +#define CHIP0_BASE (0x40 << 24) +#define CHIP1_BASE (0x60 << 24) +#else +#define CHIP0_BASE (0x20 << 24) +#define CHIP1_BASE (0x40 << 24) +#endif +#define MEMCONFIG0_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\

•                         | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
  

+#define MEMCONFIG1_VAL (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\

•                         | CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)
  

+#define TP_CNT (0xff << 24) +#define PRECHCONFIG TP_CNT

+#define CTRL_OFF (0 << 0) +#define CTRL_DLL_OFF (0 << 1) +#define CTRL_HALF (0 << 2) +#define CTRL_DFDQS (1 << 3) +#define DQS_DELAY (0 << 4) +#define CTRL_START_POINT (0x10 << 8) +#define CTRL_INC (0x10 << 16) +#define CTRL_FORCE (0x71 << 24) +#define CONTROL0_VAL (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\

•                         | CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\
  

•                         | CTRL_INC | CTRL_FORCE)
  

+#define CTRL_SHIFTC (0x6 << 0) +#define CTRL_REF (8 << 4) +#define CTRL_SHGATE (1 << 29) +#define TERM_READ_EN (1 << 30) +#define TERM_WRITE_EN (1 << 31) +#define CONTROL1_VAL (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\

•                         | TERM_READ_EN | TERM_WRITE_EN)
  

+#define CONTROL2_VAL 0x00000000

+#ifdef CONFIG_ORIGEN +#define TIMINGREF_VAL 0x000000BB +#define TIMINGROW_VAL 0x4046654f +#define TIMINGDATA_VAL 0x46400506 +#define TIMINGPOWER_VAL 0x52000A3C +#else +#define TIMINGREF_VAL 0x000000BC +#ifdef DRAM_CLK_330 +#define TIMINGROW_VAL 0x3545548d +#define TIMINGDATA_VAL 0x45430506 +#define TIMINGPOWER_VAL 0x4439033c +#endif +#ifdef DRAM_CLK_400 +#define TIMINGROW_VAL 0x45430506 +#define TIMINGDATA_VAL 0x56500506 +#define TIMINGPOWER_VAL 0x5444033d +#endif +#endif #endif diff --git a/board/samsung/smdk5250/setup.h b/arch/arm/cpu/armv7/exynos/exynos5_setup.h similarity index 96% rename from board/samsung/smdk5250/setup.h rename to arch/arm/cpu/armv7/exynos/exynos5_setup.h index eb91d13..8f36c16 100644 --- a/board/samsung/smdk5250/setup.h +++ b/arch/arm/cpu/armv7/exynos/exynos5_setup.h @@ -93,17 +93,17 @@ #define DMC_MEMCONTROL_MRR_BYTE_31_24 (3 << 25)

/* MEMCONFIG0 register bit fields */ -#define DMC_MEMCONFIGx_CHIP_MAP_INTERLEAVED (1 << 12) -#define DMC_MEMCONFIGx_CHIP_COL_10 (3 << 8) -#define DMC_MEMCONFIGx_CHIP_ROW_14 (2 << 4) -#define DMC_MEMCONFIGx_CHIP_ROW_15 (3 << 4) -#define DMC_MEMCONFIGx_CHIP_BANK_8 (3 << 0)

-#define DMC_MEMBASECONFIGx_CHIP_BASE(x) (x << 16) -#define DMC_MEMBASECONFIGx_CHIP_MASK(x) (x << 0) +#define DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED (1 << 12) +#define DMC_MEMCONFIGX_CHIP_COL_10 (3 << 8) +#define DMC_MEMCONFIGX_CHIP_ROW_14 (2 << 4) +#define DMC_MEMCONFIGX_CHIP_ROW_15 (3 << 4) +#define DMC_MEMCONFIGX_CHIP_BANK_8 (3 << 0)

+#define DMC_MEMBASECONFIGX_CHIP_BASE(x) (x << 16) +#define DMC_MEMBASECONFIGX_CHIP_MASK(x) (x << 0) #define DMC_MEMBASECONFIG_VAL(x) ( \

• DMC_MEMBASECONFIGx_CHIP_BASE(x) |       \
  

• DMC_MEMBASECONFIGx_CHIP_MASK(0x780)     \
  

• DMC_MEMBASECONFIGX_CHIP_BASE(x) |       \
  

• DMC_MEMBASECONFIGX_CHIP_MASK(0x780)     \
  

)

#define DMC_MEMBASECONFIG0_VAL DMC_MEMBASECONFIG_VAL(0x40) @@ -513,9 +513,11 @@ enum {

•               which the DMC uses to decide how to split a memory
  

•               chunk into smaller chunks to support concurrent
  

•               accesses; may vary across boards.
  

• • @param reset Reset DDR PHY during initialization.
  • @return 0 if ok, SETUP_ERR_... if there is a problem
  */

-int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size); +int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,

•                 int reset);
  
  

/*

• Configure ZQ I/O interface

@@ -562,8 +564,4 @@ void dmc_config_memory(struct mem_timings *mem, struct exynos5_dmc *dmc);

• @param ddr_mode Type of DDR memory

*/ void update_reset_dll(struct exynos5_dmc *, enum ddr_mode);

-void sdelay(unsigned long); -void mem_ctrl_init(void); -void system_clock_init(void); #endif diff --git a/arch/arm/cpu/armv7/exynos/lowlevel_init.c b/arch/arm/cpu/armv7/exynos/lowlevel_init.c new file mode 100644 index 0000000..11fe5b8 --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/lowlevel_init.c @@ -0,0 +1,73 @@ +/*

• • Lowlevel setup for EXYNOS5 based board
• • Copyright (C) 2013 Samsung Electronics
• • Rajeshwari Shinde rajeshwari.s@samsung.com
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <config.h> +#include <asm/arch/cpu.h> +#include <asm/arch/dmc.h> +#include <asm/arch/power.h> +#include <asm/arch/tzpc.h> +#include <asm/arch/periph.h> +#include <asm/arch/pinmux.h> +#include "common_setup.h"

+/* These are the things we can do during low-level init */ +enum {

• DO_WAKEUP       = 1 << 0,
  

• DO_CLOCKS       = 1 << 1,
  

• DO_MEM_RESET    = 1 << 2,
  

• DO_UART         = 1 << 3,
  

+};

+int do_lowlevel_init(void) +{

• uint32_t reset_status;
  

• int actions = 0;
  

• arch_cpu_init();
  

• reset_status = get_reset_status();
  

• switch (reset_status) {
  

• case S5P_CHECK_SLEEP:
  

•         actions = DO_CLOCKS | DO_WAKEUP;
  

•         break;
  

• case S5P_CHECK_DIDLE:
  

• case S5P_CHECK_LPA:
  

•         actions = DO_WAKEUP;
  

•         break;
  

• default:
  

•         /* This is a normal boot (not a wake from sleep) */
  

•         actions = DO_CLOCKS | DO_MEM_RESET;
  

• }
  

• if (actions & DO_CLOCKS) {
  

•         system_clock_init();
  

•         mem_ctrl_init(actions & DO_MEM_RESET);
  

•         tzpc_init();
  

• }
  

• return actions & DO_WAKEUP;
  

+} diff --git a/board/samsung/smdk5250/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c similarity index 74% rename from board/samsung/smdk5250/spl_boot.c rename to arch/arm/cpu/armv7/exynos/spl_boot.c index 83275f1..6e8dd3b 100644 --- a/board/samsung/smdk5250/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -23,13 +23,18 @@ #include<common.h> #include<config.h>

-#include <asm/arch-exynos/dmc.h> #include <asm/arch/clock.h> #include <asm/arch/clk.h> +#include <asm/arch/dmc.h> +#include <asm/arch/power.h> #include <asm/arch/spl.h>

+#include "common_setup.h" #include "clock_init.h"

+DECLARE_GLOBAL_DATA_PTR; +#define OM_STAT (0x1f << 1)

/* Index into irom ptr table */ enum index { MMC_INDEX, @@ -54,6 +59,7 @@ void *get_irom_func(int index) return (void *)*(u32 *)irom_ptr_table[index]; }

+#ifdef CONFIG_USB_BOOTING /*

• Set/clear program flow prediction and return the previous state.

*/ @@ -67,6 +73,7 @@ static int config_branch_prediction(int set_cr_z)

  return cr & CR_Z;

} +#endif

/*

• Copy U-boot from mmc to RAM:

@@ -75,35 +82,42 @@ static int config_branch_prediction(int set_cr_z) */ void copy_uboot_to_ram(void) {

• int is_cr_z_set;
  

• unsigned int sec_boot_check;
  enum boot_mode bootmode = BOOT_MODE_OM;
  
  

• u32 (*spi_copy)(u32 offset, u32 nblock, u32 dst);
  

• u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst);
  

• u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
  

• u32 offset = 0, size = 0;
  

+#ifdef CONFIG_SUPPORT_EMMC_BOOT u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst); void (*end_bootop_from_emmc)(void); +#endif +#ifdef CONFIG_USB_BOOTING u32 (*usb_copy)(void);

• int is_cr_z_set;
  

• unsigned int sec_boot_check;
  
  /* Read iRAM location to check for secondary USB boot mode */
  sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE);
  if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT)
          bootmode = BOOT_MODE_USB;
  

+#endif

  if (bootmode == BOOT_MODE_OM)

•         bootmode = readl(EXYNOS5_POWER_BASE) & OM_STAT;
  

•         bootmode = readl(samsung_get_base_power()) & OM_STAT;
  
  switch (bootmode) {
  

+#ifdef CONFIG_SPI_BOOTING case BOOT_MODE_SERIAL:

•         spi_copy = get_irom_func(SPI_INDEX);
  

•         spi_copy(SPI_FLASH_UBOOT_POS, CONFIG_BL2_SIZE,
  

•                  CONFIG_SYS_TEXT_BASE);
  

•         offset = SPI_FLASH_UBOOT_POS;
  

•         size = CONFIG_BL2_SIZE;
  

•         copy_bl2 = get_irom_func(SPI_INDEX);
          break;
  

+#endif case BOOT_MODE_MMC:

•         offset = BL2_START_OFFSET;
  

•         size = BL2_SIZE_BLOC_COUNT;
          copy_bl2 = get_irom_func(MMC_INDEX);
  

•         copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT,
  

•                  CONFIG_SYS_TEXT_BASE);
          break;
  

+#ifdef CONFIG_SUPPORT_EMMC_BOOT case BOOT_MODE_EMMC: /* Set the FSYS1 clock divisor value for EMMC boot */ emmc_boot_clk_div_set(); @@ -114,6 +128,8 @@ void copy_uboot_to_ram(void) copy_bl2_from_emmc(BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); end_bootop_from_emmc(); break; +#endif +#ifdef CONFIG_USB_BOOTING case BOOT_MODE_USB: /* * iROM needs program flow prediction to be disabled @@ -124,14 +140,50 @@ void copy_uboot_to_ram(void) usb_copy(); config_branch_prediction(is_cr_z_set); break; +#endif default: break; }

• if (copy_bl2)
  

•         copy_bl2(offset, size, CONFIG_SYS_TEXT_BASE);
  

+}

+void memzero(void *s, size_t n) +{

• char *ptr = s;
  

• size_t i;
  

• for (i = 0; i < n; i++)
  

•         *ptr++ = '\0';
  

+}

+/**

• • Set up the U-Boot global_data pointer
• • This sets the address of the global data, and sets up basic values.
• • @param gdp Value to give to gd
• */

+static void setup_global_data(gd_t *gdp) +{

• gd = gdp;
  

• memzero((void *)gd, sizeof(gd_t));
  

• gd->flags |= GD_FLG_RELOC;
  

• gd->baudrate = CONFIG_BAUDRATE;
  

• gd->have_console = 1;
  

}

void board_init_f(unsigned long bootflag) {

• __aligned(8) gd_t local_gd;
  __attribute__((noreturn)) void (*uboot)(void);
  

• setup_global_data(&local_gd);
  

• if (do_lowlevel_init())
  

•         power_exit_wakeup();
  

• copy_uboot_to_ram();
  
  /* Jump to U-Boot image */
  

diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 36b98c8..75dbe26 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -115,7 +115,7 @@ #define EXYNOS5_DMC_PHY0_BASE 0x10C00000 #define EXYNOS5_DMC_PHY1_BASE 0x10C10000

maybe it can be dmc0 and dmc1 If you want to keep the interface with exynos4.

EXYNOS4 donot have seperate Phy controller it is a part of DMC controller. then I need to add following for EXYNOS4 EXYNOS4_DMC_PHY1_BASE DEVICE_NOT_AVAILABLE EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE

...

#define EXYNOS5_GPIO_PART3_BASE 0x10D10000 -#define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 +#define EXYNOS5_DMC0_BASE 0x10DD0000

why?

if we want to make funstion to get the DMC base address it is needed to be added for EXYNOS5 as well hence made this change.

...

#define EXYNOS5_GPIO_PART1_BASE 0x11400000 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 @@ -135,6 +135,7 @@

#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE +#define EXYNOS5_DMC1_BASE DEVICE_NOT_AVAILABLE

It looks weird.

Since EXYNOS4 has 2 DMC controllers and EXYNOS5 has only 1 DMC controller I had to add this to avoid compilation error. Please do let me know if you are fine with these changes.

...

#ifndef __ASSEMBLY__ #include <asm/io.h> @@ -237,6 +238,8 @@ SAMSUNG_BASE(power, POWER_BASE) SAMSUNG_BASE(spi, SPI_BASE) SAMSUNG_BASE(spi_isp, SPI_ISP_BASE) SAMSUNG_BASE(tzpc, TZPC_BASE) +SAMSUNG_BASE(dmc0, DMC0_BASE) +SAMSUNG_BASE(dmc1, DMC1_BASE) #endif

#endif /* _EXYNOS4_CPU_H */

...

diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h index 6c7a052..b32d1bd 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-dt.h @@ -104,6 +104,7 @@

#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SKIP_LOWLEVEL_INIT

/* PWM */ #define CONFIG_PWM @@ -137,6 +138,7 @@ #define CONFIG_USB_STORAGE

/* USB boot mode */ +#define CONFIG_USB_BOOTING #define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 @@ -152,6 +154,8 @@ #define CONFIG_SPL #define COPY_BL2_FNPTR_ADDR 0x02020030

+#define CONFIG_SPL_LIBCOMMON_SUPPORT

/* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_TEXT_BASE 0x02023400 @@ -229,7 +233,7 @@ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)

-#define OM_STAT (0x1f << 1) +#define CONFIG_SPI_BOOTING #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)

@@ -241,7 +245,7 @@

#define CONFIG_IRAM_STACK 0x02050000

-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK

/* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD diff --git a/include/configs/origen.h b/include/configs/origen.h index f71a463..fd7d667 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -68,6 +68,8 @@ #define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x020000

+#define CONFIG_SKIP_LOWLEVEL_INIT

/* SD/MMC configuration */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC @@ -148,7 +150,10 @@ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) #define CONFIG_DOS_PARTITION 1

-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)

+#define CONFIG_SYS_INIT_SP_ADDR 0x02040000

/* U-boot copy size from boot Media to DRAM.*/ #define COPY_BL2_SIZE 0x80000 @@ -157,4 +162,5 @@

/* Enable devicetree support */ #define CONFIG_OF_LIBFDT

#endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index db78127..38ba292 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -58,6 +58,7 @@ /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 +#define S5P_CHECK_LPA 0xABAD0000

/* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) @@ -94,6 +95,7 @@

/* MMC SPL */ #define CONFIG_SPL +#define CONFIG_SKIP_LOWLEVEL_INIT #define COPY_BL2_FNPTR_ADDR 0x00002488

#define CONFIG_SPL_TEXT_BASE 0x02021410 @@ -147,7 +149,10 @@ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) #define CONFIG_DOS_PARTITION 1

-#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)

+#define CONFIG_SYS_INIT_SP_ADDR 0x02040000

/* U-boot copy size from boot Media to DRAM.*/ #define COPY_BL2_SIZE 0x80000

Thanks, Minkyu Kang. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot