From: Stephen Warren swarren@nvidia.com
There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs.
Signed-off-by: Stephen Warren swarren@nvidia.com Tested-by: Thierry Reding treding@nvidia.com --- v2: New patch, split out from the later Tegra124 changes. --- arch/arm/cpu/arm720t/tegra-common/cpu.c | 12 +----------- arch/arm/cpu/arm720t/tegra-common/cpu.h | 8 +++++--- 2 files changed, 6 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c index 322ce10d6fe3..d62bb9e370e0 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.c +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c @@ -315,7 +315,6 @@ void reset_A9_cpu(int reset) void clock_enable_coresight(int enable) { u32 rst, src = 2; - int soc_type;
debug("clock_enable_coresight entry\n"); clock_set_enable(PERIPH_ID_CORESIGHT, enable); @@ -328,16 +327,7 @@ void clock_enable_coresight(int enable) * Clock divider request would setup CSITE clock as 144MHz * for PLLP base 216MHz and 204MHz for PLLP base 408MHz */ - - soc_type = tegra_get_chip(); - if (soc_type == CHIPID_TEGRA30 || soc_type == CHIPID_TEGRA114) - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 204000); - else if (soc_type == CHIPID_TEGRA20) - src = CLK_DIVIDER(NVBL_PLLP_KHZ, 144000); - else - printf("%s: Unknown SoC type %X!\n", - __func__, soc_type); - + src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ); clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
/* Unlock the CPU CoreSight interfaces */ diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.h b/arch/arm/cpu/arm720t/tegra-common/cpu.h index 60412c7f87eb..d1520ce2cc88 100644 --- a/arch/arm/cpu/arm720t/tegra-common/cpu.h +++ b/arch/arm/cpu/arm720t/tegra-common/cpu.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2010-2011 + * (C) Copyright 2010-2014 * NVIDIA Corporation <www.nvidia.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -11,9 +11,11 @@ #define IO_STABILIZATION_DELAY (1000)
#if defined(CONFIG_TEGRA20) -#define NVBL_PLLP_KHZ (216000) +#define NVBL_PLLP_KHZ 216000 +#define CSITE_KHZ 144000 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) -#define NVBL_PLLP_KHZ (408000) +#define NVBL_PLLP_KHZ 408000 +#define CSITE_KHZ 204000 #else #error "Unknown Tegra chip!" #endif