26 Jul
2023
26 Jul
'23
10:09 a.m.
Hi Jagan,
On 2023/7/19 16:17, Jagan Teki wrote:
Sync the linux-next from below commit, commit <1642bf66e270> ("arm64: dts: rockchip: add USB2 to rk3588s-rock5a")
How much difference for the linux-next and the latest linux release version?
It would be better if we can have sync with a release version unless many important patches are on the way.
Also rops the duplicate usb nodes from rk3588s-u-boot.dtsi
Signed-off-by: Jagan Teki jagan@edgeble.ai
Changes for v2:
Keep sdhci modes for ROCK5B
arch/arm/dts/rk3588-edgeble-neu6a.dtsi | 1 - arch/arm/dts/rk3588-edgeble-neu6b-io.dts | 66 +++ arch/arm/dts/rk3588-edgeble-neu6b.dtsi | 359 ++++++++++- arch/arm/dts/rk3588-evb1-v10.dts | 720 ++++++++++++++++++++++- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 7 - arch/arm/dts/rk3588-rock-5b.dts | 578 +++++++++++++++++- arch/arm/dts/rk3588.dtsi | 112 ++++ arch/arm/dts/rk3588s-u-boot.dtsi | 119 ---- arch/arm/dts/rk3588s.dtsi | 499 +++++++++++++++- include/dt-bindings/ata/ahci.h | 20 +
Why need this ahci header file in the patch?
Thanks,
- Kever
10 files changed, 2346 insertions(+), 135 deletions(-) create mode 100644 include/dt-bindings/ata/ahci.h
diff --git a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi index 38e1a1e25f..727580aaa1 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6a.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6a.dtsi @@ -25,7 +25,6 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay";
diff --git a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts index e9d5a8bab5..9933765e40 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b-io.dts +++ b/arch/arm/dts/rk3588-edgeble-neu6b-io.dts @@ -21,7 +21,73 @@ }; };
+&combphy0_ps {
- status = "okay";
+};
+&i2c6 {
- status = "okay";
- hym8563: rtc@51 {
compatible = "haoyu,hym8563";reg = <0x51>;interrupt-parent = <&gpio0>;interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;#clock-cells = <0>;clock-output-names = "hym8563";pinctrl-names = "default";pinctrl-0 = <&hym8563_int>;wakeup-source;- };
+};
+&pinctrl {
- hym8563 {
hym8563_int: hym8563-int {rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+/* FAN */ +&pwm2 {
- pinctrl-0 = <&pwm2m1_pins>;
- pinctrl-names = "default";
- status = "okay";
+};
+&sata0 {
- status = "okay";
+};
+&sdmmc {
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- no-sdio;
- no-mmc;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+/* RS232 */ +&uart6 {
- pinctrl-0 = <&uart6m0_xfer>;
- pinctrl-names = "default";
- status = "okay";
+};
+/* RS485 */ +&uart7 {
- pinctrl-0 = <&uart7m2_xfer>;
- pinctrl-names = "default";
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi index 1c5bcf1280..017559bba3 100644 --- a/arch/arm/dts/rk3588-edgeble-neu6b.dtsi +++ b/arch/arm/dts/rk3588-edgeble-neu6b.dtsi @@ -18,6 +18,42 @@ regulator-min-microvolt = <12000000>; regulator-max-microvolt = <12000000>; };
- vcc5v0_sys: vcc5v0-sys-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_sys";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_1v1_nldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;vin-supply = <&vcc5v0_sys>;- };
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>; };
&sdhci {
@@ -25,8 +61,329 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- pmic@0 {
compatible = "rockchip,rk806";spi-max-frequency = <1000000>;reg = <0x0>;interrupt-parent = <&gpio0>;interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;gpio-controller;#gpio-cells = <2>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {regulator-name = "vdd_gpu_s0";regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {regulator-name = "vdd_cpu_lit_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-name = "vdd_log_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {regulator-name = "vdd_vdenc_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-init-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg5 {regulator-name = "vdd_ddr_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};vdd2_ddr_s3: dcdc-reg6 {regulator-name = "vdd2_ddr_s3";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-on-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-name = "vdd_2v0_pldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vcc_3v3_s3: dcdc-reg8 {regulator-name = "vcc_3v3_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vddq_ddr_s0: dcdc-reg9 {regulator-name = "vddq_ddr_s0";regulator-always-on;regulator-boot-on;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s3: dcdc-reg10 {regulator-name = "vcc_1v8_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_s0: pldo-reg1 {regulator-name = "avcc_1v8_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: pldo-reg2 {regulator-name = "vcc_1v8_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1800000>;};};avdd_1v2_s0: pldo-reg3 {regulator-name = "avdd_1v2_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: pldo-reg4 {regulator-name = "vcc_3v3_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};vccio_sd_s0: pldo-reg5 {regulator-name = "vccio_sd_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-name = "pldo6_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-name = "vdd_0v75_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-name = "vdd_ddr_pll_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};avdd_0v75_s0: nldo-reg3 {regulator-name = "avdd_0v75_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg4 {regulator-name = "vdd_0v85_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-state-mem {regulator-off-in-suspend;};};vdd_0v75_s0: nldo-reg5 {regulator-name = "vdd_0v75_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-state-mem {regulator-off-in-suspend;};};};- };
+}; diff --git a/arch/arm/dts/rk3588-evb1-v10.dts b/arch/arm/dts/rk3588-evb1-v10.dts index b91af0204d..229a9111f5 100644 --- a/arch/arm/dts/rk3588-evb1-v10.dts +++ b/arch/arm/dts/rk3588-evb1-v10.dts @@ -38,6 +38,20 @@ regulator-max-microvolt = <12000000>; };
- vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-boot-on;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_usb>;- };
- vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys";
@@ -47,6 +61,62 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc12v_dcin>; };
- vcc5v0_usbdcin: vcc5v0-usbdcin-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usbdcin";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc12v_dcin>;- };
- vcc5v0_usb: vcc5v0-usb-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_usb";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;vin-supply = <&vcc5v0_usbdcin>;- };
+};
+&combphy0_ps {
- status = "okay";
+};
+&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>; };
&gmac0 {
@@ -106,6 +176,12 @@ rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; }; };
usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};}; };
&pwm2 {
@@ -117,13 +193,655 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- num-cs = <2>;
- pmic@0 {
compatible = "rockchip,rk806";reg = <0x0>;#gpio-cells = <2>;gpio-controller;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;pinctrl-names = "default";spi-max-frequency = <1000000>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc5v0_sys>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl1";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: dcdc-reg1 {regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_gpu_s0";regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_npu_s0: dcdc-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_npu_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_log_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: dcdc-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_vdenc_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_gpu_mem_s0: dcdc-reg5 {regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-enable-ramp-delay = <400>;regulator-name = "vdd_gpu_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_npu_mem_s0: dcdc-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_npu_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_2v0_pldo_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vdd_vdenc_mem_s0: dcdc-reg8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_vdenc_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd2_ddr_s3: dcdc-reg9 {regulator-always-on;regulator-boot-on;regulator-name = "vdd2_ddr_s3";regulator-state-mem {regulator-on-in-suspend;};};vcc_1v1_nldo_s3: dcdc-reg10 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_1v1_nldo_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1100000>;};};avcc_1v8_s0: pldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "avcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd1_1v8_ddr_s3: pldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vdd1_1v8_ddr_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_codec_s0: pldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "avcc_1v8_codec_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s3: pldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vccio_sd_s0: pldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vccio_sd_s0";regulator-state-mem {regulator-off-in-suspend;};};vccio_1v8_s3: pldo-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vccio_1v8_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_0v75_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd2l_0v9_ddr_s3: nldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <900000>;regulator-max-microvolt = <900000>;regulator-name = "vdd2l_0v9_ddr_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <900000>;};};vdd_0v75_hdmi_edp_s0: nldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "vdd_0v75_hdmi_edp_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_0v75_s0: nldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "avdd_0v75_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_0v85_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
- pmic@1 {
compatible = "rockchip,rk806";reg = <0x01>;#gpio-cells = <2>;gpio-controller;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>,<&rk806_slave_dvs3_null>;pinctrl-names = "default";spi-max-frequency = <1000000>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_2v0_pldo_s3>;vcca-supply = <&vcc5v0_sys>;rk806_slave_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl1";function = "pin_fun0";};rk806_slave_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_slave_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_cpu_big1_s0: dcdc-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big1_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_big0_s0: dcdc-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big0_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: dcdc-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_lit_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: dcdc-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_big1_mem_s0: dcdc-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big1_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_big0_mem_s0: dcdc-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_big0_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: dcdc-reg7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_mem_s0: dcdc-reg8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_lit_mem_s0";regulator-state-mem {regulator-off-in-suspend;};};vddq_ddr_s0: dcdc-reg9 {regulator-always-on;regulator-boot-on;regulator-name = "vddq_ddr_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg10 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_ddr_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_cam_s0: pldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_1v8_cam_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd1v8_ddr_pll_s0: pldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "avdd1v8_ddr_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_1v8_pll_s0: pldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_1v8_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_sd_s0: pldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_sd_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_2v8_cam_s0: pldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2800000>;regulator-max-microvolt = <2800000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_2v8_cam_s0";regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "pldo6_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_pll_s0: nldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_0v75_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_ddr_pll_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_0v85_s0: nldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-ramp-delay = <12500>;regulator-name = "avdd_0v85_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_1v2_cam_s0: nldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-ramp-delay = <12500>;regulator-name = "avdd_1v2_cam_s0";regulator-state-mem {regulator-off-in-suspend;};};avdd_1v2_s0: nldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-ramp-delay = <12500>;regulator-name = "avdd_1v2_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
+&sata0 {
- status = "okay";
+};
+&u2phy2 {
- status = "okay";
+};
+&u2phy2_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&u2phy3 {
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 1cd8a57a6f..bfa560ca5f 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -99,11 +99,6 @@ bootph-all; };
-&sdmmc {
- bus-width = <4>;
- status = "okay";
-};
- &sdmmc_bus4 { bootph-all; };
@@ -124,8 +119,6 @@ cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v;
pinctrl-names = "default";
pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_data_strobe &emmc_rstnout>; };
&sfc {
diff --git a/arch/arm/dts/rk3588-rock-5b.dts b/arch/arm/dts/rk3588-rock-5b.dts index 95805cb0ad..49d5eb8862 100644 --- a/arch/arm/dts/rk3588-rock-5b.dts +++ b/arch/arm/dts/rk3588-rock-5b.dts @@ -2,6 +2,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h> #include "rk3588.dtsi"
/ { @@ -17,6 +18,45 @@ stdout-path = "serial2:1500000n8"; };
- analog-sound {
compatible = "audio-graph-card";label = "rk3588-es8316";widgets = "Microphone", "Mic Jack","Headphone", "Headphones";routing = "MIC2", "Mic Jack","Headphones", "HPOL","Headphones", "HPOR";dais = <&i2s0_8ch_p0>;hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&hp_detect>;- };
- fan: pwm-fan {
compatible = "pwm-fan";cooling-levels = <0 95 145 195 255>;fan-supply = <&vcc5v0_sys>;pwms = <&pwm1 0 50000 0>;#cooling-cells = <2>;- };
- vcc5v0_host: vcc5v0-host-regulator {
compatible = "regulator-fixed";regulator-name = "vcc5v0_host";regulator-boot-on;regulator-always-on;regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;enable-active-high;gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;pinctrl-names = "default";pinctrl-0 = <&vcc5v0_host_en>;vin-supply = <&vcc5v0_sys>;- };
- vcc5v0_sys: vcc5v0-sys-regulator { compatible = "regulator-fixed"; regulator-name = "vcc5v0_sys";
@@ -25,6 +65,171 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; };
- vcc_1v1_nldo_s3: vcc-1v1-nldo-s3-regulator {
compatible = "regulator-fixed";regulator-name = "vcc_1v1_nldo_s3";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1100000>;regulator-max-microvolt = <1100000>;vin-supply = <&vcc5v0_sys>;- };
+};
+&cpu_b0 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b1 {
- cpu-supply = <&vdd_cpu_big0_s0>;
+};
+&cpu_b2 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_b3 {
- cpu-supply = <&vdd_cpu_big1_s0>;
+};
+&cpu_l0 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l1 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l2 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&cpu_l3 {
- cpu-supply = <&vdd_cpu_lit_s0>;
+};
+&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0m2_xfer>;
- status = "okay";
- vdd_cpu_big0_s0: regulator@42 {
compatible = "rockchip,rk8602";reg = <0x42>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu_big0_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <2300>;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
- vdd_cpu_big1_s0: regulator@43 {
compatible = "rockchip,rk8603", "rockchip,rk8602";reg = <0x43>;fcs,suspend-voltage-selector = <1>;regulator-name = "vdd_cpu_big1_s0";regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <1050000>;regulator-ramp-delay = <2300>;vin-supply = <&vcc5v0_sys>;regulator-state-mem {regulator-off-in-suspend;};- };
+};
+&i2c6 {
- status = "okay";
- hym8563: rtc@51 {
compatible = "haoyu,hym8563";reg = <0x51>;#clock-cells = <0>;clock-output-names = "hym8563";pinctrl-names = "default";pinctrl-0 = <&hym8563_int>;interrupt-parent = <&gpio0>;interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;wakeup-source;- };
+};
+&i2c7 {
- status = "okay";
- es8316: audio-codec@11 {
compatible = "everest,es8316";reg = <0x11>;clocks = <&cru I2S0_8CH_MCLKOUT>;clock-names = "mclk";assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;assigned-clock-rates = <12288000>;#sound-dai-cells = <0>;port {es8316_p0_0: endpoint {remote-endpoint = <&i2s0_8ch_p0_0>;};};- };
+};
+&i2s0_8ch {
- pinctrl-names = "default";
- pinctrl-0 = <&i2s0_lrck
&i2s0_mclk&i2s0_sclk&i2s0_sdi0&i2s0_sdo0>;- status = "okay";
- i2s0_8ch_p0: port {
i2s0_8ch_p0_0: endpoint {dai-format = "i2s";mclk-fs = <256>;remote-endpoint = <&es8316_p0_0>;};- };
+};
+&pinctrl {
- hym8563 {
hym8563_int: hym8563-int {rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- sound {
hp_detect: hp-detect {rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;};- };
- usb {
vcc5v0_host_en: vcc5v0-host-en {rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;};- };
+};
+&pwm1 {
- status = "okay";
+};
+&saradc {
vref-supply = <&avcc_1v8_s0>;
status = "okay"; };
&sdhci {
@@ -32,13 +237,384 @@ no-sdio; no-sd; non-removable;
- max-frequency = <200000000>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; status = "okay"; };
+&sdmmc {
- max-frequency = <200000000>;
- no-sdio;
- no-mmc;
- bus-width = <4>;
- cap-mmc-highspeed;
- cap-sd-highspeed;
- disable-wp;
- sd-uhs-sdr104;
- vmmc-supply = <&vcc_3v3_s3>;
- vqmmc-supply = <&vccio_sd_s0>;
- status = "okay";
+};
+&spi2 {
- status = "okay";
- assigned-clocks = <&cru CLK_SPI2>;
- assigned-clock-rates = <200000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
- num-cs = <1>;
- pmic@0 {
compatible = "rockchip,rk806";spi-max-frequency = <1000000>;reg = <0x0>;interrupt-parent = <&gpio0>;interrupts = <7 IRQ_TYPE_LEVEL_LOW>;pinctrl-names = "default";pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,<&rk806_dvs2_null>, <&rk806_dvs3_null>;vcc1-supply = <&vcc5v0_sys>;vcc2-supply = <&vcc5v0_sys>;vcc3-supply = <&vcc5v0_sys>;vcc4-supply = <&vcc5v0_sys>;vcc5-supply = <&vcc5v0_sys>;vcc6-supply = <&vcc5v0_sys>;vcc7-supply = <&vcc5v0_sys>;vcc8-supply = <&vcc5v0_sys>;vcc9-supply = <&vcc5v0_sys>;vcc10-supply = <&vcc5v0_sys>;vcc11-supply = <&vcc_2v0_pldo_s3>;vcc12-supply = <&vcc5v0_sys>;vcc13-supply = <&vcc_1v1_nldo_s3>;vcc14-supply = <&vcc_1v1_nldo_s3>;vcca-supply = <&vcc5v0_sys>;gpio-controller;#gpio-cells = <2>;rk806_dvs1_null: dvs1-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs2_null: dvs2-null-pins {pins = "gpio_pwrctrl2";function = "pin_fun0";};rk806_dvs3_null: dvs3-null-pins {pins = "gpio_pwrctrl3";function = "pin_fun0";};regulators {vdd_gpu_s0: vdd_gpu_mem_s0: dcdc-reg1 {regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_gpu_s0";regulator-enable-ramp-delay = <400>;regulator-state-mem {regulator-off-in-suspend;};};vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_cpu_lit_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_log_s0: dcdc-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <750000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_log_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <550000>;regulator-max-microvolt = <950000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_vdenc_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_ddr_s0: dcdc-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <675000>;regulator-max-microvolt = <900000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_ddr_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};vdd2_ddr_s3: dcdc-reg6 {regulator-always-on;regulator-boot-on;regulator-name = "vdd2_ddr_s3";regulator-state-mem {regulator-on-in-suspend;};};vcc_2v0_pldo_s3: dcdc-reg7 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <2000000>;regulator-max-microvolt = <2000000>;regulator-ramp-delay = <12500>;regulator-name = "vdd_2v0_pldo_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <2000000>;};};vcc_3v3_s3: dcdc-reg8 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc_3v3_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <3300000>;};};vddq_ddr_s0: dcdc-reg9 {regulator-always-on;regulator-boot-on;regulator-name = "vddq_ddr_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s3: dcdc-reg10 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_1v8_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};avcc_1v8_s0: pldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "avcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_1v8_s0: pldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc_1v8_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <1800000>;};};avdd_1v2_s0: pldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-name = "avdd_1v2_s0";regulator-state-mem {regulator-off-in-suspend;};};vcc_3v3_s0: pldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vcc_3v3_s0";regulator-state-mem {regulator-off-in-suspend;};};vccio_sd_s0: pldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;regulator-ramp-delay = <12500>;regulator-name = "vccio_sd_s0";regulator-state-mem {regulator-off-in-suspend;};};pldo6_s3: pldo-reg6 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "pldo6_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <1800000>;};};vdd_0v75_s3: nldo-reg1 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "vdd_0v75_s3";regulator-state-mem {regulator-on-in-suspend;regulator-suspend-microvolt = <750000>;};};vdd_ddr_pll_s0: nldo-reg2 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_ddr_pll_s0";regulator-state-mem {regulator-off-in-suspend;regulator-suspend-microvolt = <850000>;};};avdd_0v75_s0: nldo-reg3 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "avdd_0v75_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_0v85_s0: nldo-reg4 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <850000>;regulator-max-microvolt = <850000>;regulator-name = "vdd_0v85_s0";regulator-state-mem {regulator-off-in-suspend;};};vdd_0v75_s0: nldo-reg5 {regulator-always-on;regulator-boot-on;regulator-min-microvolt = <750000>;regulator-max-microvolt = <750000>;regulator-name = "vdd_0v75_s0";regulator-state-mem {regulator-off-in-suspend;};};};- };
+};
- &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; };
+&u2phy2 {
- status = "okay";
+};
+&u2phy2_host {
- /* connected to USB hub, which is powered by vcc5v0_sys */
- phy-supply = <&vcc5v0_sys>;
- status = "okay";
+};
+&u2phy3 {
- status = "okay";
+};
+&u2phy3_host {
- phy-supply = <&vcc5v0_host>;
- status = "okay";
+};
+&usb_host0_ehci {
- status = "okay";
+};
+&usb_host0_ohci {
- status = "okay";
+};
+&usb_host1_ehci {
- status = "okay";
+};
+&usb_host1_ohci {
- status = "okay";
+}; diff --git a/arch/arm/dts/rk3588.dtsi b/arch/arm/dts/rk3588.dtsi index d085e57fbc..6be9bf81c0 100644 --- a/arch/arm/dts/rk3588.dtsi +++ b/arch/arm/dts/rk3588.dtsi @@ -7,6 +7,79 @@ #include "rk3588-pinctrl.dtsi"
/ {
- pipe_phy1_grf: syscon@fd5c0000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";reg = <0x0 0xfd5c0000 0x0 0x100>;- };
- i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddc8000 0x0 0x1000>;interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 22>;dma-names = "tx";power-domains = <&power RK3588_PD_VO0>;resets = <&cru SRST_M_I2S8_8CH_TX>;reset-names = "tx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s6_8ch: i2s@fddf4000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddf4000 0x0 0x1000>;interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 4>;dma-names = "tx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S6_8CH_TX>;reset-names = "tx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s7_8ch: i2s@fddf8000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddf8000 0x0 0x1000>;interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 21>;dma-names = "rx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S7_8CH_RX>;reset-names = "rx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s10_8ch: i2s@fde00000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfde00000 0x0 0x1000>;interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 24>;dma-names = "rx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S10_8CH_RX>;reset-names = "rx-m";#sound-dai-cells = <0>;status = "disabled";- };
- gmac0: ethernet@fe1b0000 { compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; reg = <0x0 0xfe1b0000 0x0 0x10000>;
@@ -55,4 +128,43 @@ queue1 {}; }; };
- sata1: sata@fe220000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";reg = <0 0xfe220000 0 0x1000>;interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,<&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,<&cru CLK_PIPEPHY1_PIPE_ASIC_G>;clock-names = "sata", "pmalive", "rxoob", "ref", "asic";ports-implemented = <0x1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";sata-port@0 {reg = <0>;hba-port-cap = <HBA_PORT_FBSCP>;phys = <&combphy1_ps PHY_TYPE_SATA>;phy-names = "sata-phy";snps,rx-ts-max = <32>;snps,tx-ts-max = <32>;};- };
- combphy1_ps: phy@fee10000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee10000 0x0 0x100>;clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,<&cru PCLK_PHP_ROOT>;clock-names = "ref", "apb", "pipe";assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;assigned-clock-rates = <100000000>;#phy-cells = <1>;resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;reset-names = "phy", "apb";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy1_grf>;status = "disabled";- }; };
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi index c703e41802..f8c10227b0 100644 --- a/arch/arm/dts/rk3588s-u-boot.dtsi +++ b/arch/arm/dts/rk3588s-u-boot.dtsi @@ -13,103 +13,12 @@ status = "okay"; };
usb_host0_ehci: usb@fc800000 {
compatible = "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
usb_host0_ohci: usb@fc840000 {
compatible = "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
usb_host1_ehci: usb@fc880000 {
compatible = "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
usb_host1_ohci: usb@fc8c0000 {
compatible = "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;clock-names = "usbhost", "arbiter";power-domains = <&power RK3588_PD_USB>;status = "disabled";};
pmu1_grf: syscon@fd58a000 { bootph-all; compatible = "rockchip,rk3588-pmu1-grf", "syscon"; reg = <0x0 0xfd58a000 0x0 0x2000>; };
pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;};
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};};
usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon","simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};};
pcie2x1l2: pcie@fe190000 { compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; #address-cells = <3>;
@@ -174,39 +83,11 @@ status = "disabled"; };
otp: nvmem@fecc0000 {
compatible = "rockchip,rk3588-otp";reg = <0x0 0xfecc0000 0x0 0x400>;#address-cells = <1>;#size-cells = <1>;status = "okay";cpu_id: id@7 {reg = <0x07 0x10>;};};
rng: rng@fe378000 { compatible = "rockchip,trngv1"; reg = <0x0 0xfe378000 0x0 0x200>; status = "disabled"; };
combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;#phy-cells = <1>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,<&cru PCLK_PHP_ROOT>;clock-names = "refclk", "apbclk", "phpclk";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>;reset-names = "combphy-apb", "combphy";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";}; };
&xin24m {
diff --git a/arch/arm/dts/rk3588s.dtsi b/arch/arm/dts/rk3588s.dtsi index fca8503aed..c9f9dd2472 100644 --- a/arch/arm/dts/rk3588s.dtsi +++ b/arch/arm/dts/rk3588s.dtsi @@ -8,6 +8,8 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/power/rk3588-power.h> #include <dt-bindings/reset/rockchip,rk3588-cru.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/ata/ahci.h>
/ { compatible = "rockchip,rk3588"; @@ -60,6 +62,8 @@ enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>;@@ -136,6 +140,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>;@@ -174,6 +180,8 @@ enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;assigned-clock-rates = <816000000>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>;@@ -222,6 +230,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -230,6 +240,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -238,6 +250,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -246,6 +260,8 @@ cache-size = <131072>; cache-line-size = <64>; cache-sets = <512>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -254,6 +270,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -262,6 +280,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -270,6 +290,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -278,6 +300,8 @@ cache-size = <524288>; cache-line-size = <64>; cache-sets = <1024>;
cache-level = <2>;cache-unified; next-level-cache = <&l3_cache>;@@ -286,6 +310,8 @@ cache-size = <3145728>; cache-line-size = <64>; cache-sets = <4096>;
cache-level = <3>;cache-unified;@@ -304,10 +330,6 @@
scmi_clk: protocol@14 { reg = <0x14>;
assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,<&scmi_clk SCMI_CLK_CPUB23>;assigned-clock-rates = <1200000000>,<1200000000>; #clock-cells = <1>; };@@ -377,6 +399,50 @@ }; };
- usb_host0_ehci: usb@fc800000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";reg = <0x0 0xfc800000 0x0 0x40000>;interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;phys = <&u2phy2_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host0_ohci: usb@fc840000 {
compatible = "rockchip,rk3588-ohci", "generic-ohci";reg = <0x0 0xfc840000 0x0 0x40000>;interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;phys = <&u2phy2_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ehci: usb@fc880000 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";reg = <0x0 0xfc880000 0x0 0x40000>;interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;phys = <&u2phy3_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- usb_host1_ohci: usb@fc8c0000 {
compatible = "rockchip,rk3588-ohci", "generic-ohci";reg = <0x0 0xfc8c0000 0x0 0x40000>;interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;phys = <&u2phy3_host>;phy-names = "usb";power-domains = <&power RK3588_PD_USB>;status = "disabled";- };
- sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>;
@@ -387,6 +453,66 @@ reg = <0x0 0xfd5b0000 0x0 0x1000>; };
- pipe_phy0_grf: syscon@fd5bc000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";reg = <0x0 0xfd5bc000 0x0 0x100>;- };
- pipe_phy2_grf: syscon@fd5c4000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";reg = <0x0 0xfd5c4000 0x0 0x100>;- };
- usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";reg = <0x0 0xfd5d8000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy2: usb2-phy@8000 {compatible = "rockchip,rk3588-usb2phy";reg = <0x8000 0x10>;interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;reset-names = "phy", "apb";clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";clock-output-names = "usb480m_phy2";#clock-cells = <0>;status = "disabled";u2phy2_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- usb2phy3_grf: syscon@fd5dc000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";reg = <0x0 0xfd5dc000 0x0 0x4000>;#address-cells = <1>;#size-cells = <1>;u2phy3: usb2-phy@c000 {compatible = "rockchip,rk3588-usb2phy";reg = <0xc000 0x10>;interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;reset-names = "phy", "apb";clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;clock-names = "phyclk";clock-output-names = "usb480m_phy3";#clock-cells = <0>;status = "disabled";u2phy3_host: host-port {#phy-cells = <0>;status = "disabled";};};- };
- ioc: syscon@fd5f0000 { compatible = "rockchip,rk3588-ioc", "syscon"; reg = <0x0 0xfd5f0000 0x0 0x10000>;
@@ -414,7 +540,7 @@ <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, <&cru CLK_GPU>; assigned-clock-rates =
<100000000>, <786432000>,
<1100000000>, <786432000>, <850000000>, <1188000000>, <702000000>, <400000000>, <500000000>,@@ -810,6 +936,57 @@ }; };
- i2s4_8ch: i2s@fddc0000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddc0000 0x0 0x1000>;interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 0>;dma-names = "tx";power-domains = <&power RK3588_PD_VO0>;resets = <&cru SRST_M_I2S4_8CH_TX>;reset-names = "tx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s5_8ch: i2s@fddf0000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddf0000 0x0 0x1000>;interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 2>;dma-names = "tx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S5_8CH_TX>;reset-names = "tx-m";#sound-dai-cells = <0>;status = "disabled";- };
- i2s9_8ch: i2s@fddfc000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfddfc000 0x0 0x1000>;interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac2 23>;dma-names = "rx";power-domains = <&power RK3588_PD_VO1>;resets = <&cru SRST_M_I2S9_8CH_RX>;reset-names = "rx-m";#sound-dai-cells = <0>;status = "disabled";- };
- qos_gpu_m0: qos@fdf35000 { compatible = "rockchip,rk3588-qos", "syscon"; reg = <0x0 0xfdf35000 0x0 0x20>;
@@ -1099,6 +1276,52 @@ }; };
- sata0: sata@fe210000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";reg = <0 0xfe210000 0 0x1000>;interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,<&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,<&cru CLK_PIPEPHY0_PIPE_ASIC_G>;clock-names = "sata", "pmalive", "rxoob", "ref", "asic";ports-implemented = <0x1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";sata-port@0 {reg = <0>;hba-port-cap = <HBA_PORT_FBSCP>;phys = <&combphy0_ps PHY_TYPE_SATA>;phy-names = "sata-phy";snps,rx-ts-max = <32>;snps,tx-ts-max = <32>;};- };
- sata2: sata@fe230000 {
compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";reg = <0 0xfe230000 0 0x1000>;interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,<&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,<&cru CLK_PIPEPHY2_PIPE_ASIC_G>;clock-names = "sata", "pmalive", "rxoob", "ref", "asic";ports-implemented = <0x1>;#address-cells = <1>;#size-cells = <0>;status = "disabled";sata-port@0 {reg = <0>;hba-port-cap = <HBA_PORT_FBSCP>;phys = <&combphy2_psu PHY_TYPE_SATA>;phy-names = "sata-phy";snps,rx-ts-max = <32>;snps,tx-ts-max = <32>;};- };
- sdmmc: mmc@fe2c0000 { compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xfe2c0000 0x0 0x4000>;
@@ -1114,6 +1337,21 @@ status = "disabled"; };
- sdio: mmc@fe2d0000 {
compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";reg = <0x00 0xfe2d0000 0x00 0x4000>;interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";fifo-depth = <0x100>;max-frequency = <200000000>;pinctrl-names = "default";pinctrl-0 = <&sdiom1_pins>;power-domains = <&power RK3588_PD_SDIO>;status = "disabled";- };
- sdhci: mmc@fe2e0000 { compatible = "rockchip,rk3588-dwcmshc"; reg = <0x0 0xfe2e0000 0x0 0x10000>;
@@ -1125,6 +1363,9 @@ <&cru TMCLK_EMMC>; clock-names = "core", "bus", "axi", "block", "timer"; max-frequency = <200000000>;
pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,<&emmc_cmd>, <&emmc_data_strobe>;pinctrl-names = "default";@@ -1132,6 +1373,103 @@ status = "disabled"; };
- i2s0_8ch: i2s@fe470000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfe470000 0x0 0x1000>;interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;dmas = <&dmac0 0>, <&dmac0 1>;dma-names = "tx", "rx";power-domains = <&power RK3588_PD_AUDIO>;resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;reset-names = "tx-m", "rx-m";rockchip,trcm-sync-tx-only;pinctrl-names = "default";pinctrl-0 = <&i2s0_lrck&i2s0_sclk&i2s0_sdi0&i2s0_sdi1&i2s0_sdi2&i2s0_sdi3&i2s0_sdo0&i2s0_sdo1&i2s0_sdo2&i2s0_sdo3>;#sound-dai-cells = <0>;status = "disabled";- };
- i2s1_8ch: i2s@fe480000 {
compatible = "rockchip,rk3588-i2s-tdm";reg = <0x0 0xfe480000 0x0 0x1000>;interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;clock-names = "mclk_tx", "mclk_rx", "hclk";dmas = <&dmac0 2>, <&dmac0 3>;dma-names = "tx", "rx";resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;reset-names = "tx-m", "rx-m";rockchip,trcm-sync-tx-only;pinctrl-names = "default";pinctrl-0 = <&i2s1m0_lrck&i2s1m0_sclk&i2s1m0_sdi0&i2s1m0_sdi1&i2s1m0_sdi2&i2s1m0_sdi3&i2s1m0_sdo0&i2s1m0_sdo1&i2s1m0_sdo2&i2s1m0_sdo3>;#sound-dai-cells = <0>;status = "disabled";- };
- i2s2_2ch: i2s@fe490000 {
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";reg = <0x0 0xfe490000 0x0 0x1000>;interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;clock-names = "i2s_clk", "i2s_hclk";assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac1 0>, <&dmac1 1>;dma-names = "tx", "rx";power-domains = <&power RK3588_PD_AUDIO>;rockchip,trcm-sync-tx-only;pinctrl-names = "default";pinctrl-0 = <&i2s2m1_lrck&i2s2m1_sclk&i2s2m1_sdi&i2s2m1_sdo>;#sound-dai-cells = <0>;status = "disabled";- };
- i2s3_2ch: i2s@fe4a0000 {
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";reg = <0x0 0xfe4a0000 0x0 0x1000>;interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;clock-names = "i2s_clk", "i2s_hclk";assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;assigned-clock-parents = <&cru PLL_AUPLL>;dmas = <&dmac1 2>, <&dmac1 3>;dma-names = "tx", "rx";power-domains = <&power RK3588_PD_AUDIO>;rockchip,trcm-sync-tx-only;pinctrl-names = "default";pinctrl-0 = <&i2s3_lrck&i2s3_sclk&i2s3_sdi&i2s3_sdo>;#sound-dai-cells = <0>;status = "disabled";- };
- gic: interrupt-controller@fe600000 { compatible = "arm,gic-v3"; reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
@@ -1141,7 +1479,24 @@ mbi-alias = <0x0 0xfe610000>; mbi-ranges = <424 56>; msi-controller;
ranges;#address-cells = <2>;#interrupt-cells = <4>;
#size-cells = <2>;its0: msi-controller@fe640000 {compatible = "arm,gic-v3-its";reg = <0x0 0xfe640000 0x0 0x20000>;msi-controller;#msi-cells = <1>;};its1: msi-controller@fe660000 {compatible = "arm,gic-v3-its";reg = <0x0 0xfe660000 0x0 0x20000>;msi-controller;#msi-cells = <1>;};ppi-partitions { ppi_partition0: interrupt-partition-0 {
@@ -1241,6 +1596,22 @@ status = "disabled"; };
- timer0: timer@feae0000 {
compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";reg = <0x0 0xfeae0000 0x0 0x20>;interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;clock-names = "pclk", "timer";- };
- wdt: watchdog@feaf0000 {
compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";reg = <0x0 0xfeaf0000 0x0 0x100>;clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;clock-names = "tclk", "pclk";interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;- };
- spi0: spi@feb00000 { compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi"; reg = <0x0 0xfeb00000 0x0 0x1000>;
@@ -1572,6 +1943,38 @@ status = "disabled"; };
- tsadc: tsadc@fec00000 {
compatible = "rockchip,rk3588-tsadc";reg = <0x0 0xfec00000 0x0 0x400>;interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;clock-names = "tsadc", "apb_pclk";assigned-clocks = <&cru CLK_TSADC>;assigned-clock-rates = <2000000>;resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;reset-names = "tsadc-apb", "tsadc";rockchip,hw-tshut-temp = <120000>;rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */pinctrl-0 = <&tsadc_gpio_func>;pinctrl-1 = <&tsadc_shut>;pinctrl-names = "gpio", "otpout";#thermal-sensor-cells = <1>;status = "disabled";- };
- saradc: adc@fec10000 {
compatible = "rockchip,rk3588-saradc";reg = <0x0 0xfec10000 0x0 0x10000>;interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;#io-channel-cells = <1>;clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;clock-names = "saradc", "apb_pclk";resets = <&cru SRST_P_SARADC>;reset-names = "saradc-apb";status = "disabled";- };
- i2c6: i2c@fec80000 { compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; reg = <0x0 0xfec80000 0x0 0x1000>;
@@ -1627,6 +2030,60 @@ status = "disabled"; };
- otp: efuse@fecc0000 {
compatible = "rockchip,rk3588-otp";reg = <0x0 0xfecc0000 0x0 0x400>;clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,<&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;clock-names = "otp", "apb_pclk", "phy", "arb";resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,<&cru SRST_OTPC_ARB>;reset-names = "otp", "apb", "arb";#address-cells = <1>;#size-cells = <1>;cpu_code: cpu-code@2 {reg = <0x02 0x2>;};otp_id: id@7 {reg = <0x07 0x10>;};cpub0_leakage: cpu-leakage@17 {reg = <0x17 0x1>;};cpub1_leakage: cpu-leakage@18 {reg = <0x18 0x1>;};cpul_leakage: cpu-leakage@19 {reg = <0x19 0x1>;};log_leakage: log-leakage@1a {reg = <0x1a 0x1>;};gpu_leakage: gpu-leakage@1b {reg = <0x1b 0x1>;};otp_cpu_version: cpu-version@1c {reg = <0x1c 0x1>;bits = <3 3>;};npu_leakage: npu-leakage@28 {reg = <0x28 0x1>;};codec_leakage: codec-leakage@29 {reg = <0x29 0x1>;};- };
- dmac2: dma-controller@fed10000 { compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0xfed10000 0x0 0x4000>;
@@ -1638,6 +2095,38 @@ #dma-cells = <1>; };
- combphy0_ps: phy@fee00000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee00000 0x0 0x100>;clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,<&cru PCLK_PHP_ROOT>;clock-names = "ref", "apb", "pipe";assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;assigned-clock-rates = <100000000>;#phy-cells = <1>;resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;reset-names = "phy", "apb";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy0_grf>;status = "disabled";- };
- combphy2_psu: phy@fee20000 {
compatible = "rockchip,rk3588-naneng-combphy";reg = <0x0 0xfee20000 0x0 0x100>;clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,<&cru PCLK_PHP_ROOT>;clock-names = "ref", "apb", "pipe";assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;assigned-clock-rates = <100000000>;#phy-cells = <1>;resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;reset-names = "phy", "apb";rockchip,pipe-grf = <&php_grf>;rockchip,pipe-phy-grf = <&pipe_phy2_grf>;status = "disabled";- };
- system_sram2: sram@ff001000 { compatible = "mmio-sram"; reg = <0x0 0xff001000 0x0 0xef000>;
diff --git a/include/dt-bindings/ata/ahci.h b/include/dt-bindings/ata/ahci.h new file mode 100644 index 0000000000..77997b3561 --- /dev/null +++ b/include/dt-bindings/ata/ahci.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */ +/*
- This header provides constants for most AHCI bindings.
- */
+#ifndef _DT_BINDINGS_ATA_AHCI_H +#define _DT_BINDINGS_ATA_AHCI_H
+/* Host Bus Adapter generic platform capabilities */ +#define HBA_SSS (1 << 27) +#define HBA_SMPS (1 << 28)
+/* Host Bus Adapter port-specific platform capabilities */ +#define HBA_PORT_HPCP (1 << 18) +#define HBA_PORT_MPSP (1 << 19) +#define HBA_PORT_CPD (1 << 20) +#define HBA_PORT_ESP (1 << 21) +#define HBA_PORT_FBSCP (1 << 22)
+#endif