22 Oct
2014
22 Oct
'14
8:07 p.m.
On Wed, 2014-10-22 at 16:47 +0800, Chen-Yu Tsai wrote:
From: Hans de Goede hdegoede@redhat.com
The A31, A23 and later SoCs have an extra pin controller, called CPUs_PIO or R_PIO, which handles pin banks L and beyond.
Also add a clear description about SUNXI_GPIO_BANKS, stating it only counts the number of pin banks in the _main_ pin controller.
Signed-off-by: Hans de Goede hdegoede@redhat.com [wens@csie.org: expanded commit message] [wens@csie.org: add pin bank M and expand comments] [wens@csie.org: add comment on SUNXI_GPIO_BANKS macro] Signed-off-by: Chen-Yu Tsai wens@csie.org
Acked-by: Ian Campbell ijc@hellion.org.uk