Re: [PATCH 2/2] armv8/cache.S: Triple with single instruction

On Fri, Aug 27, 2021 at 06:04:10PM +0200, Pierre-Clément Tosi wrote:

Replace the current 2-instruction 2-step tripling code by a corresponding single instruction leveraging ARMv8-A's "flexible second operand as a register with optional shift". This has the added benefit (albeit arguably negligible) of reducing the final code size.

Fix the comment as the tripled cache level is placed in x12, not x0.

Signed-off-by: Pierre-Clément Tosi ptosi@google.com

Applied to u-boot/next, thanks!