Re: [U-Boot-Users] [PATCH] 7450 and 86xx L2 cache invalidate bug corrections

4 May 2008


      Dear Jon,
in message BAFDFD588011D0429A8CE7E0A0EB23F8031F4798@az33exm21.fsl.freescale.net
Travis Wheatley wrote:
...
The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.
This patch addresses both of these bugs.
Will you please ACK this patch?
Best regards,
Wolfgang Denk
-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
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