Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng.cn@gmail.com wrote:
device.h for integrated pci devices' bdf on Quark SoC and quark.h for various memory-mapped and i/o-mapped base addresses within SoC.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/include/asm/arch-quark/device.h | 28 ++++++++++++++++ arch/x86/include/asm/arch-quark/quark.h | 57 ++++++++++++++++++++++++++++++++ 2 files changed, 85 insertions(+) create mode 100644 arch/x86/include/asm/arch-quark/device.h create mode 100644 arch/x86/include/asm/arch-quark/quark.h
diff --git a/arch/x86/include/asm/arch-quark/device.h b/arch/x86/include/asm/arch-quark/device.h new file mode 100644 index 0000000..4af3ded --- /dev/null +++ b/arch/x86/include/asm/arch-quark/device.h @@ -0,0 +1,28 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _QUARK_DEVICE_H_ +#define _QUARK_DEVICE_H_
+#include <pci.h>
+#define QUARK_HOST_BRIDGE PCI_BDF(0, 0, 0) +#define QUARK_MMC_SDIO PCI_BDF(0, 20, 0) +#define QUARK_UART0 PCI_BDF(0, 20, 1) +#define QUARK_USB_DEVICE PCI_BDF(0, 20, 2) +#define QUARK_USB_EHCI PCI_BDF(0, 20, 3) +#define QUARK_USB_OHCI PCI_BDF(0, 20, 4) +#define QUARK_UART1 PCI_BDF(0, 20, 5) +#define QUARK_EMAC0 PCI_BDF(0, 20, 6) +#define QUARK_EMAC1 PCI_BDF(0, 20, 7) +#define QUARK_SPI0 PCI_BDF(0, 21, 0) +#define QUARK_SPI1 PCI_BDF(0, 21, 1) +#define QUARK_I2C_GPIO PCI_BDF(0, 21, 2) +#define QUARK_PCIE0 PCI_BDF(0, 23, 0) +#define QUARK_PCIE1 PCI_BDF(0, 23, 1) +#define QUARK_LEGACY_BRIDGE PCI_BDF(0, 31, 0)
+#endif /* _QUARK_DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-quark/quark.h b/arch/x86/include/asm/arch-quark/quark.h new file mode 100644 index 0000000..6eef2d1 --- /dev/null +++ b/arch/x86/include/asm/arch-quark/quark.h @@ -0,0 +1,57 @@ +/*
- Copyright (C) 2015, Bin Meng bmeng.cn@gmail.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _QUARK_H_ +#define _QUARK_H_
+/* The following are Memory Base Addresses */
+/* DRAM */ +#define DRAM_BASE 0x00000000 +#define DRAM_MAX_SIZE 0x80000000
+/* eSRAM */ +#define ESRAM_BASE (DRAM_BASE + DRAM_MAX_SIZE) +#define ESRAM_SIZE 0x80000
+/* SMM Control */
+/* PCIe ECAM */ +#define PCIE_ECAM_BASE 0xE0000000
Can we use lower case hex?
I suppose this one will move to Kconfig before we apply it?
What about the others?
+/* RCBA */ +#define RCBA_BASE 0xFED1C000
+/* Memory BAR Enable */ +#define MEM_BAR_EN 0x00000001
+/* 64KiB of RMU binary in flash */ +#define RMU_BINARY_SIZE 0x10000
+/* The following are I/O Base Addresses */
+/* ACPI PM1 Block */ +#define ACPI_PM1_BASE 0x1000
+/* ACPI P Block */ +#define ACPI_P_BASE 0x1010
+/* SPI DMA */ +#define SPI_DMA_BASE 0x1020
+/* GPIO */ +#define GPIO_BASE 0x1080
+/* GPE0 */ +#define GPE0_BASE 0x1100
+/* WDT */ +#define WDT_BASE 0x1140
+/* I/O BAR Enable */ +#define IO_BAR_EN 0x80000000
+#endif /* _QUARK_H_ */
1.8.2.1
Regards, Simon