On Tuesday 18 April 2017 07:03 PM, Lukasz Majewski wrote:
Hi Ravi,
From: Lokesh Vutla lokeshvutla@ti.com
Declare the size of ddr very early in spl, so that this can be used to enable cache.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: Ravi Babu ravibabu@ti.com
arch/arm/mach-omap2/am33xx/board.c | 4 ++++ arch/arm/mach-omap2/hwinit-common.c | 1 + 2 files changed, 5 insertions(+)
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 2bfc864..568f36f 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -327,6 +327,10 @@ void board_init_f(ulong dummy) early_system_init(); board_early_init_f(); sdram_init();
- /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size(
(void *)CONFIG_SYS_SDRAM_BASE,CONFIG_MAX_RAM_BANK_SIZE);The above call is a bit strange, since the sdram_init() function sets the DDR (EMIF) controller to use the whole SDRAM available.
Why one cannot take this info directly from EMIF controller?
I guess you are talking about calling omap_sdram_size() which uses DMM to determine the DDR mapped sections. There is no DMM for amx3xx SoCs. Also get_ram_size() checks memory range for valid RAM. A simple memory test determines the actually available RAM size between addresses `base' and `base + maxsize' and widely being used by entire U-Boot.
Thanks and regards, Lokesh