Re: [U-Boot] [PATCH v5 075/101] spi: ich: Add TPL support

Hi Simon,

On Mon, Nov 25, 2019 at 12:12 PM Simon Glass sjg@chromium.org wrote:

In TPL we want to reduce code size and support running with CONFIG_PCI disabled. Add special code to handle this using a fixed BAR programmed into the SPI on boot. Also cache the SPI flash to speed up boot.

Signed-off-by: Simon Glass sjg@chromium.org

Changes in v5: None Changes in v4: None Changes in v3: None Changes in v2: None

drivers/spi/ich.c | 46 ++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 42 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index ebf369f215..02601e9125 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -19,8 +19,10 @@ #include <spi.h> #include <spi_flash.h> #include <spi-mem.h> +#include <spl.h> #include <asm/fast_spi.h> #include <asm/io.h> +#include <asm/mtrr.h>

#include "ich.h"

@@ -115,6 +117,8 @@ static bool ich9_can_do_33mhz(struct udevice *dev) struct ich_spi_priv *priv = dev_get_priv(dev); u32 fdod, speed;

•   if (!CONFIG_IS_ENABLED(PCI))
  

•           return false;
    /* Observe SPI Descriptor Component Section 0 */
    dm_pci_write_config32(priv->pch, 0xb0, 0x1000);
  
  

@@ -706,6 +710,15 @@ static int ich_init_controller(struct udevice *dev, struct ich_spi_platdata *plat, struct ich_spi_priv *ctlr) {

•   if (spl_phase() == PHASE_TPL) {
  

•           struct ich_spi_platdata *plat = dev_get_platdata(dev);
  

•           int ret;
  

•           ret = fast_spi_early_init(plat->bdf, plat->mmio_base);
  

•           if (ret)
  

•                   return ret;
  

•   }
  

•   ctlr->base = (void *)plat->mmio_base;
    if (plat->ich_version == ICHV_7) {
            struct ich7_spi_regs *ich7_spi = ctlr->base;
  

@@ -754,6 +767,25 @@ static int ich_init_controller(struct udevice *dev, return 0; }

+static int ich_cache_bios_region(struct udevice *dev) +{

•   ulong map_base;
  

•   uint map_size;
  

•   uint offset;
  

•   ulong base;
  

•   int ret;
  

•   ret = ich_get_mmap_bus(dev, &map_base, &map_size, &offset);
  

•   if (ret)
  

•           return ret;
  

•   base = (4ULL << 30) - map_size;
  

Can we define a macro for this? MEM_4G?

•   mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
  

Should this be MTRR_TYPE_WRBACK?

•   log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
  

•   return 0;
  

+}

static int ich_spi_probe(struct udevice *dev) { struct ich_spi_platdata *plat = dev_get_platdata(dev); @@ -764,10 +796,16 @@ static int ich_spi_probe(struct udevice *dev) if (ret) return ret;

•   ret = ich_protect_lockdown(dev);
  

•   if (ret)
  

•           return ret;
  

•   if (spl_phase() == PHASE_TPL) {
  

•           /* Cache the BIOS to speed things up */
  

•           ret = ich_cache_bios_region(dev);
  

•           if (ret)
  

•                   return ret;
  

•   } else {
  

•           ret = ich_protect_lockdown(dev);
  

•           if (ret)
  

•                   return ret;
  

•   }
    priv->cur_speed = priv->max_speed;
  
    return 0;
  

--

Regards, Bin