-----Original Message----- From: York Sun Sent: Thursday, November 09, 2017 2:02 AM To: Rajesh Bhagat rajesh.bhagat@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Priyanka Jain priyanka.jain@nxp.com; Ashish Kumar ashish.kumar@nxp.com Subject: Re: [PATCH v4 1/7] armv8: lsch3: Add serdes and DDR voltage setup
On 11/07/2017 02:37 AM, Rajesh Bhagat wrote:
Adds SERDES voltage and reset SERDES lanes API and makes enable/disable DDR controller support 0.9V API common.
Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com Signed-off-by: Rajesh Bhagat rajesh.bhagat@nxp.com
Changes in v4:
- Added local macros instead of magical numbers
- Created macros to remove duplicate code
Changes in v3: Restructured LS1088A VID support to use common VID driver Cosmetic review comments fixed Added __iomem for accessing registers
Changes in v2: Checkpatch errors fixed
.../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c | 263
+++++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 34 +-- .../include/asm/arch-fsl-layerscape/fsl_serdes.h | 2 +- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 34 +++ arch/arm/include/asm/arch-fsl-layerscape/soc.h | 1 + 5 files changed, 316 insertions(+), 18 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 179cac6..6fbfbed 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -158,6 +158,269 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32
sd_prctl_mask,
serdes_prtcl_map[NONE] = 1; }
+__weak int get_serdes_volt(void) +{
- return -1;
+}
+__weak int set_serdes_volt(int svdd) +{
- return -1;
+}
+#define LNAGCR0_RESET_MASK 0xFF9FFFFF +#define LNAGCR0_RT_RSTB 0x00600000 +#define RSTCTL_RESET_MASK_1 0xFFFFFFBF +#define RSTCTL_RESET_MASK_2 0xFFFFFF1F +#define RSTCTL_RESET_MASK_3 0xFFFFFFEF +#define RSTCTL_RSTREQ 0x80000000 +#define RSTCTL_RSTERR 0x20000000 +#define RSTCTL_SDEN 0x00000020 +#define RSTCTL_SDRST_B 0x00000040 +#define RSTCTL_PLLRST_B 0x00000080 +#define RSTCTL_RST_DONE 0x40000000 +#define TCALCR_RESET_MASK 0xF7FFFFFF +#define TCALCR_CALRST_B 0x08000000
+#define CAT2(x, y) CAT2_(x, y) +#define CAT2_(x, y) x ## y
+#define CAT3(x, y, z) CAT3_(x, y, z) +#define CAT3_(x, y, z) x ## y ## z
+#define DO_ENABLED_LANES_RESET(x) do { \
- cfg_tmp = CAT2(cfg_rcwsrds, x) & \
CAT3(FSL_CHASSIS3_SRDS, x, _PRTCL_MASK); \- cfg_tmp >>= CAT3(FSL_CHASSIS3_SRDS, x, _PRTCL_SHIFT); \
\- for (i = 0; i < 4 && cfg_tmp & (0xf << (3 - i)); i++) { \
reg = in_le32(&CAT3(serdes, x, _base)->lane[i].gcr0); \reg &= LNAGCR0_RESET_MASK; \out_le32(&CAT3(serdes, x, _base)->lane[i].gcr0, reg); \- } \
+} while (0)
I don't like these macros. They break grep-ability. I understand you are trying to simply the code and reuse. There are other technique to do the same. I personally would use local functions with pointers to deal with serdes base, and use array to handle things like FSL_CHASSIS3_SRDS1_PRTCL_SHIFT and masks.
Will take care in v5
- Rajesh
York