From: Jagan Teki jagan@amarulasolutions.com
Boot from MMC: ------------- U-Boot SPL 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44) Trying to boot from MMC1
U-Boot 2016.11-rc2-g217bd8e-dirty (Nov 08 2016 - 22:59:44 +0530)
CPU: Freescale i.MX6D rev1.2 at 792 MHz Reset cause: POR Model: Engicam i.CoreM6 Quad/Dual RQS Starter Kit DRAM: 512 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment
In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 icorem6qdl-rqs>
Cc: Stefano Babic sbabic@denx.de Cc: Matteo Lisi matteo.lisi@engicam.com Cc: Michael Trimarchi michael@amarulasolutions.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- arch/arm/cpu/armv7/mx6/Kconfig | 11 + arch/arm/dts/Makefile | 1 + arch/arm/dts/imx6q-icore-rqs.dts | 50 ++++ arch/arm/dts/imx6qdl-icore-rqs.dtsi | 83 +++++++ board/engicam/icorem6_rqs/Kconfig | 12 + board/engicam/icorem6_rqs/MAINTAINERS | 6 + board/engicam/icorem6_rqs/Makefile | 6 + board/engicam/icorem6_rqs/README | 30 +++ board/engicam/icorem6_rqs/icorem6_rqs.c | 399 ++++++++++++++++++++++++++++++++ configs/imx6q_icore_rqs_mmc_defconfig | 38 +++ include/configs/imx6qdl_icore_rqs.h | 124 ++++++++++ 11 files changed, 760 insertions(+) create mode 100644 arch/arm/dts/imx6q-icore-rqs.dts create mode 100644 arch/arm/dts/imx6qdl-icore-rqs.dtsi create mode 100644 board/engicam/icorem6_rqs/Kconfig create mode 100644 board/engicam/icorem6_rqs/MAINTAINERS create mode 100644 board/engicam/icorem6_rqs/Makefile create mode 100644 board/engicam/icorem6_rqs/README create mode 100644 board/engicam/icorem6_rqs/icorem6_rqs.c create mode 100644 configs/imx6q_icore_rqs_mmc_defconfig create mode 100644 include/configs/imx6qdl_icore_rqs.h
diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 30a13c2..fc12d65 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -107,6 +107,16 @@ config TARGET_MX6Q_ICORE select DM_THERMAL select SUPPORT_SPL
+config TARGET_MX6Q_ICORE_RQS + bool "Support Engicam i.Core RQS" + select MX6QDL + select OF_CONTROL + select DM + select DM_GPIO + select DM_MMC + select DM_THERMAL + select SUPPORT_SPL + config TARGET_MX6QSABREAUTO bool "mx6qsabreauto" select DM @@ -250,6 +260,7 @@ source "board/el/el6x/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/engicam/geam6ul/Kconfig" source "board/engicam/icorem6/Kconfig" +source "board/engicam/icorem6_rqs/Kconfig" source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6qsabreauto/Kconfig" source "board/freescale/mx6sabresd/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d79b2e2..be38c83 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -285,6 +285,7 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6dl-icore.dtb \ imx6q-icore.dtb \ + imx6q-icore-rqs.dtb \ imx6ul-geam-kit.dtb
dtb-$(CONFIG_MX7) += imx7-colibri.dtb diff --git a/arch/arm/dts/imx6q-icore-rqs.dts b/arch/arm/dts/imx6q-icore-rqs.dts new file mode 100644 index 0000000..9fa6ba0 --- /dev/null +++ b/arch/arm/dts/imx6q-icore-rqs.dts @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-icore-rqs.dtsi" + +/ { + model = "Engicam i.CoreM6 Quad/Dual RQS Starter Kit"; + compatible = "engicam,imx6-icore-rqs", "fsl,imx6q"; +}; diff --git a/arch/arm/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/dts/imx6qdl-icore-rqs.dtsi new file mode 100644 index 0000000..343ab35 --- /dev/null +++ b/arch/arm/dts/imx6qdl-icore-rqs.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015 Amarula Solutions B.V. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +/ { + memory { + reg = <0x10000000 0x80000000>; + }; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17070 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10070 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17070 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17070 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17070 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17070 + >; + }; +}; diff --git a/board/engicam/icorem6_rqs/Kconfig b/board/engicam/icorem6_rqs/Kconfig new file mode 100644 index 0000000..1352c68 --- /dev/null +++ b/board/engicam/icorem6_rqs/Kconfig @@ -0,0 +1,12 @@ +if TARGET_MX6Q_ICORE_RQS + +config SYS_BOARD + default "icorem6_rqs" + +config SYS_VENDOR + default "engicam" + +config SYS_CONFIG_NAME + default "imx6qdl_icore_rqs" + +endif diff --git a/board/engicam/icorem6_rqs/MAINTAINERS b/board/engicam/icorem6_rqs/MAINTAINERS new file mode 100644 index 0000000..4c6bd62 --- /dev/null +++ b/board/engicam/icorem6_rqs/MAINTAINERS @@ -0,0 +1,6 @@ +ICOREM6QDL_RQS BOARD +M: Jagan Teki jagan@amarulasolutions.com +S: Maintained +F: board/engicam/icorem6_rqs +F: include/configs/imx6qdl_icore_rqs.h +F: configs/imx6q_icore_rqs_mmc_defconfig diff --git a/board/engicam/icorem6_rqs/Makefile b/board/engicam/icorem6_rqs/Makefile new file mode 100644 index 0000000..2e3933c --- /dev/null +++ b/board/engicam/icorem6_rqs/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2016 Amarula Solutions B.V. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := icorem6_rqs.o diff --git a/board/engicam/icorem6_rqs/README b/board/engicam/icorem6_rqs/README new file mode 100644 index 0000000..f94e6e1 --- /dev/null +++ b/board/engicam/icorem6_rqs/README @@ -0,0 +1,30 @@ +How to use U-Boot on Engicam i.CoreM6 RQS Quad/Dual Starter Kit: +---------------------------------------------------------------- + +$ make mrproper + +- Configure U-Boot for Engicam i.CoreM6 RQS Quad/Dual: +$ make imx6q_icore_rqs_mmc_defconfig + +- Build U-Boot +$ make + +This will generate the SPL image called SPL and the u-boot-dtb.img. + +- Flash the SPL image into the micro SD card: + +sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync + +- Flash the u-boot-dtb.img image into the micro SD card: + +sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync + +- Jumper settings: + +MMC Boot: JM3 Closed + +- Connect the Serial cable between the Starter Kit and the PC for the console. +(J28 is the Linux Serial console connector) + +- Insert the micro SD card in the board, power it up and U-Boot messages should +come up. diff --git a/board/engicam/icorem6_rqs/icorem6_rqs.c b/board/engicam/icorem6_rqs/icorem6_rqs.c new file mode 100644 index 0000000..2769177 --- /dev/null +++ b/board/engicam/icorem6_rqs/icorem6_rqs.c @@ -0,0 +1,399 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * Author: Jagan Teki jagan@amarulasolutions.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <asm/io.h> +#include <asm/gpio.h> +#include <linux/sizes.h> + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/iomux-v3.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const uart4_pads[] = { + IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), + IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), +}; + +int board_early_init_f(void) +{ + SETUP_IOMUX_PADS(uart4_pads); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <libfdt.h> +#include <spl.h> + +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-ddr.h> + +/* MMC board initialization is needed till adding DM support in SPL */ +#if defined(CONFIG_FSL_ESDHC) && !defined(CONFIG_DM_MMC) +#include <mmc.h> +#include <fsl_esdhc.h> + +#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +static iomux_v3_cfg_t const usdhc3_pads[] = { + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), +}; + +struct fsl_esdhc_cfg usdhc_cfg[1] = { + {USDHC3_BASE_ADDR, 1, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC3_BASE_ADDR: + ret = 1; + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 USDHC3 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + SETUP_IOMUX_PADS(usdhc3_pads); + usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + break; + default: + printf("Warning - USDHC%d controller not supporting\n", + i + 1); + return 0; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) { + printf("Warning: failed to initialize mmc dev %d\n", i); + return ret; + } + } + + return 0; +} +#endif + +/* + * Driving strength: + * 0x30 == 40 Ohm + * 0x28 == 48 Ohm + */ + +#define IMX6DQ_DRIVE_STRENGTH 0x30 +#define IMX6SDL_DRIVE_STRENGTH 0x28 + +/* configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + .dram_sdqs0 = 0x28, + .dram_sdqs1 = 0x28, + .dram_sdqs2 = 0x28, + .dram_sdqs3 = 0x28, + .dram_sdqs4 = 0x28, + .dram_sdqs5 = 0x28, + .dram_sdqs6 = 0x28, + .dram_sdqs7 = 0x28, + .dram_dqm0 = 0x28, + .dram_dqm1 = 0x28, + .dram_dqm2 = 0x28, + .dram_dqm3 = 0x28, + .dram_dqm4 = 0x28, + .dram_dqm5 = 0x28, + .dram_dqm6 = 0x28, + .dram_dqm7 = 0x28, + .dram_cas = 0x30, + .dram_ras = 0x30, + .dram_sdclk_0 = 0x30, + .dram_sdclk_1 = 0x30, + .dram_reset = 0x30, + .dram_sdcke0 = 0x3000, + .dram_sdcke1 = 0x3000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x30, + .dram_sdodt1 = 0x30, +}; + +/* configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + .grp_b0ds = 0x30, + .grp_b1ds = 0x30, + .grp_b2ds = 0x30, + .grp_b3ds = 0x30, + .grp_b4ds = 0x30, + .grp_b5ds = 0x30, + .grp_b6ds = 0x30, + .grp_b7ds = 0x30, + .grp_addds = 0x30, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_ctlds = 0x30, + .grp_ddr_type = 0x000c0000, +}; + +/* configure MX6SOLO/DUALLITE mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + .dram_sdclk_0 = 0x30, + .dram_sdclk_1 = 0x30, + .dram_cas = 0x30, + .dram_ras = 0x30, + .dram_reset = 0x30, + .dram_sdcke0 = 0x30, + .dram_sdcke1 = 0x30, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x30, + .dram_sdodt1 = 0x30, + .dram_sdqs0 = 0x28, + .dram_sdqs1 = 0x28, + .dram_sdqs2 = 0x28, + .dram_sdqs3 = 0x28, + .dram_sdqs4 = 0x28, + .dram_sdqs5 = 0x28, + .dram_sdqs6 = 0x28, + .dram_sdqs7 = 0x28, + .dram_dqm0 = 0x28, + .dram_dqm1 = 0x28, + .dram_dqm2 = 0x28, + .dram_dqm3 = 0x28, + .dram_dqm4 = 0x28, + .dram_dqm5 = 0x28, + .dram_dqm6 = 0x28, + .dram_dqm7 = 0x28, +}; + +/* configure MX6SOLO/DUALLITE mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x30, + .grp_ctlds = 0x30, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x28, + .grp_b1ds = 0x28, + .grp_b2ds = 0x28, + .grp_b3ds = 0x28, + .grp_b4ds = 0x28, + .grp_b5ds = 0x28, + .grp_b6ds = 0x28, + .grp_b7ds = 0x28, +}; + +/* mt41j256 */ +static struct mx6_ddr3_cfg mt41j256 = { + .mem_speed = 1066, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 13, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 0, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + .p0_mpwldectrl0 = 0x000E0009, + .p0_mpwldectrl1 = 0x0018000E, + .p1_mpwldectrl0 = 0x00000007, + .p1_mpwldectrl1 = 0x00000000, + .p0_mpdgctrl0 = 0x43280334, + .p0_mpdgctrl1 = 0x031C0314, + .p1_mpdgctrl0 = 0x4318031C, + .p1_mpdgctrl1 = 0x030C0258, + .p0_mprddlctl = 0x3E343A40, + .p1_mprddlctl = 0x383C3844, + .p0_mpwrdlctl = 0x40404440, + .p1_mpwrdlctl = 0x4C3E4446, +}; + +/* DDR 64bit */ +static struct mx6_ddr_sysinfo mem_q = { + .ddr_type = DDR_TYPE_DDR3, + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 2, + .rtt_wr = 2, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static struct mx6_mmdc_calibration mx6dl_mmdc_calib = { + .p0_mpwldectrl0 = 0x001F0024, + .p0_mpwldectrl1 = 0x00110018, + .p1_mpwldectrl0 = 0x001F0024, + .p1_mpwldectrl1 = 0x00110018, + .p0_mpdgctrl0 = 0x4230022C, + .p0_mpdgctrl1 = 0x02180220, + .p1_mpdgctrl0 = 0x42440248, + .p1_mpdgctrl1 = 0x02300238, + .p0_mprddlctl = 0x44444A48, + .p1_mprddlctl = 0x46484A42, + .p0_mpwrdlctl = 0x38383234, + .p1_mpwrdlctl = 0x3C34362E, +}; + +/* DDR 64bit 1GB */ +static struct mx6_ddr_sysinfo mem_dl = { + .dsize = 2, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +/* DDR 32bit 512MB */ +static struct mx6_ddr_sysinfo mem_s = { + .dsize = 1, + .cs1_mirror = 0, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, + .ncs = 1, + .bi_on = 1, + .rtt_nom = 1, + .rtt_wr = 1, + .ralat = 5, + .walat = 0, + .mif3_mode = 3, + .rst_to_cke = 0x23, + .sde_to_rst = 0x10, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00003F3F, &ccm->CCGR0); + writel(0x0030FC00, &ccm->CCGR1); + writel(0x000FC000, &ccm->CCGR2); + writel(0x3F300000, &ccm->CCGR3); + writel(0xFF00F300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003CC, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +static void spl_dram_init(void) +{ + if (is_mx6solo()) { + mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_s, &mx6dl_mmdc_calib, &mt41j256); + } else if (is_mx6dl()) { + mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&mem_dl, &mx6dl_mmdc_calib, &mt41j256); + } else if (is_mx6dq()) { + mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&mem_q, &mx6dq_mmdc_calib, &mt41j256); + } + + udelay(100); +} + +void board_init_f(ulong dummy) +{ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + gpr_init(); + + /* iomux */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/configs/imx6q_icore_rqs_mmc_defconfig b/configs/imx6q_icore_rqs_mmc_defconfig new file mode 100644 index 0000000..eeecef8 --- /dev/null +++ b/configs/imx6q_icore_rqs_mmc_defconfig @@ -0,0 +1,38 @@ +CONFIG_ARM=y +CONFIG_ARCH_MX6=y +CONFIG_TARGET_MX6Q_ICORE_RQS=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_MMC" +CONFIG_DEFAULT_FDT_FILE="imx6q-icore-rqs.dtb" +CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore-rqs" +CONFIG_SYS_PROMPT="icorem6qdl-rqs> " +CONFIG_SPL=y +CONFIG_BOOTDELAY=3 +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTO_COMPLETE=y +CONFIG_SYS_MAXARGS=32 +# CONFIG_CMD_IMLS is not set +# CONFIG_BLK is not set +# CONFIG_DM_MMC_OPS is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MMC=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_LIBFDT=y +CONFIG_MXC_UART=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_EXT_SUPPORT=y diff --git a/include/configs/imx6qdl_icore_rqs.h b/include/configs/imx6qdl_icore_rqs.h new file mode 100644 index 0000000..7960355 --- /dev/null +++ b/include/configs/imx6qdl_icore_rqs.h @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * Configuration settings for the Engicam i.CoreM6 QDL RQS Starter Kits. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __IMX6QLD_ICORE_RQS_CONFIG_H +#define __IMX6QLD_ICORE_RQS_CONFIG_H + +#include <linux/sizes.h> +#include "mx6_common.h" + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE SZ_128K + +/* Allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Environment */ +#ifndef CONFIG_ENV_IS_NOWHERE +/* Environment in MMC */ +# if defined(CONFIG_ENV_IS_IN_MMC) +# define CONFIG_ENV_OFFSET 0x100000 +# endif +#endif + +/* Default environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "image=zImage\0" \ + "console=ttymxc3\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x18000000\0" \ + "boot_fdt=try\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "mmcautodetect=yes\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootz ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "fi; " \ + "fi; " \ + "fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_SP_OFFSET) + +/* UART */ +#ifdef CONFIG_MXC_UART +# define CONFIG_MXC_UART_BASE UART4_BASE +#endif + +/* MMC */ +#ifdef CONFIG_FSL_USDHC +# define CONFIG_SYS_MMC_ENV_DEV 0 +# define CONFIG_SYS_FSL_USDHC_NUM 1 +# define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#endif + +/* SPL */ +#ifdef CONFIG_SPL +# define CONFIG_SPL_MMC_SUPPORT +# include "imx6_spl.h" +# ifdef CONFIG_SPL_BUILD +# undef CONFIG_DM_GPIO +# undef CONFIG_DM_MMC +# endif +#endif + +#endif /* __IMX6QLD_ICORE_RQS_CONFIG_H */