1 Feb
2017
1 Feb
'17
5:10 p.m.
On 01/16/2017 11:34 PM, Mario Six wrote:
The r1 register is modified several times during the cache-ram setup of the MPC83xx SoCs.
Since this SP modification confuses debuggers, we use a general purpose register to compute the new stack pointer value, and only set the SP once after all computations are done.
Signed-off-by: Mario Six mario.six@gdsys.cc
Changes in v2:
Patch added (following a suggestion by Joakim Tjernlund)
Applied to u-boot-mpc85xx master, awaiting upstream. Thanks.
York