On Wed, 19 May 2021 21:42:06 +0200 Andreas Rehn rehn.andreas86@gmail.com wrote:
Hi,
Driver uses pinmux instead of emac type. Add v3s pinmux to support SoC.
So if I understand this correctly, then the v3s does NOT expose the MAC pins (MII/RMII/RGMII) on its package (only the V3 does this)? Instead there are internal pins, connecting the MAC directly to the internal PHY only. Those don't need to be muxed, so do not require a pinctrl-0 property.
So this whole patch would not be necessary.
If you want to avoid the message, please send a patch for that.
Cheers, Andre
Signed-off-by: Andreas Rehn rehn.andreas86@gmail.com
drivers/net/sun8i_emac.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 5a1b38bf80..0e7ad3b0d4 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -89,6 +89,7 @@ #define SUN8I_IOMUX_R40 5 #define SUN8I_IOMUX_H6 5 #define SUN8I_IOMUX_H616 2 +#define SUN8I_IOMUX_V3S 2 #define SUN8I_IOMUX 4
/* H3/A64 EMAC Register's offset */ @@ -566,6 +567,8 @@ static int parse_phy_pins(struct udevice *dev) iomux = SUN8I_IOMUX; else if (IS_ENABLED(CONFIG_MACH_SUN50I)) iomux = SUN8I_IOMUX;
- else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S))
iomux = SUN8I_IOMUX_V3S;