Hi,
I am working on system, which has chip set same as what is there in sc520_cdp board. In sc520_cdp board, for memory initialization, to write to DRAM control register they are writing to addr 0x0fffef010, for DRAM timing control register addr 0x0fffef012 and for DRAM bank configuration register addr 0x0fffef014 is used. (In file cpu/i386/sc520_asm. S) But according MCH manual these registers are PCI registers and can be accessed via CONFIG_ADDRESS and CONFIG_DATA, located at I/O addr 0xCF8 and 0xCFC respectively. Can anyone explain me, how actually in sc520_cdp board they’re are using the addr 0x0fffef012 for DRAM register and so on.
Thanks, Mushtaq Khan
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