3 Aug
2015
3 Aug
'15
1:36 a.m.
On 2 August 2015 at 15:21, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 30 July 2015 at 22:01, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Fri, Jul 31, 2015 at 3:53 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 30 July 2015 at 04:49, Bin Meng bmeng.cn@gmail.com wrote:
Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
arch/x86/cpu/baytrail/valleyview.c | 8 +++++ arch/x86/dts/bayleybay.dts | 63 ++++++++++++++++++++++++++++++++++++++ configs/bayleybay_defconfig | 2 ++ include/configs/bayleybay.h | 1 + 4 files changed, 74 insertions(+)
[snip]
Applied to u-boot-x86, thanks!