Dear Andreas,
In message 201112201339.39460.schnitzeltony@gmx.de you wrote:
I don't know if I want to jump also into these changes now - especially since I am quite new here.. But for my intererst - since it seems more error tolerant: How is SDRAM timing set up without exactly knowing what type is connected? Is there a good example implementation in u-boot(-spl)?
In most cases thare is not an arbitrary range of RAM types, but only a pretty small selection; even more often they differ only in size, not in timings. It depends on the set of possible configurations and capabilities of the meory controller how to proceed then. Typically you will start with very conservative settings, and from the sizes found you will know the correct configuration.
As for examples: probably not much in SPL, but a number of PPC board use this. See for example "board/tqc/tqm8xx/tqm8xx.c" which probes several banks of memory in 8, 9, and 10 column mode and then adjusts timing, even taking into account that the CPU and bus clock (and thus the refresh timings) are variable on some of these boards (you can set the CPU clock through the "cpuclk" environment variable).
Best regards,
Wolfgang Denk