Stefan Roese sr@denx.de schrieb am Mo., 6. Aug. 2018, 17:29:
On 06.08.2018 17:27, Simon Goldschmidt wrote:
Stefan Roese <sr@denx.de mailto:sr@denx.de> schrieb am Mo., 6. Aug. 2018, 17:23:
Hi Simon, On 06.08.2018 17:15, Simon Goldschmidt wrote: > > > Stefan Roese <sr@denx.de <mailto:sr@denx.de> <mailto:sr@denx.de <mailto:sr@denx.de>>> schrieb am Mo., 6. Aug. > 2018, 16:34: > > Some SPI NOR chips only support 4-byte mode addressing. Here the default > 3-byte mode does not work and leads to incorrect accesses. Setting this > option enables the use of such SPI NOR chips, that only support this > 4-byte mode. > > > I think it would make more sense to enable 4-byte mode or 4-byte opcodes > on all chips with more than 16 mbyte rather than having to selectat
> compile time. We need to be careful here. As setting the chip into 4-byte mode unconditionally (for bigger devices) will very likely cause boot problems with internal bootROMs expecting 3-byte mode.I have a similar problem on socfpga where Linux 4.9 sets the chip into 4-byte mode and SPL cannot use it on warm reboot. However, the bootROM does not run on warm reboot on this platform.
So in your "warm reboot" case, my option b) below would help, right?
Yes, I guess it would.
An even better idea would be to use stateless 4-byte opcodes. That's what Linux does in more recent versions. But that would be a larger patch, I guess. And with Jagan's bigger rework in his queue, I can't tell if this is a good time to do so.
b) Another idea would be to check the 3-byte / 4-byte mode of the SPI NOR device upon SPI NOR driver loading and use the selected mode accordingly. This could be done without compile time options but it would not help in general for users with bigger SPI NOR devices that support both modes.
Thanks, Stefan