The watchdog can be reset later in the LPC init() call. Move it.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/ivybridge/early_init.c | 16 ---------------- arch/x86/cpu/ivybridge/lpc.c | 12 ++++++++++++ 2 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/arch/x86/cpu/ivybridge/early_init.c b/arch/x86/cpu/ivybridge/early_init.c index 83ef7b7..5b16abc 100644 --- a/arch/x86/cpu/ivybridge/early_init.c +++ b/arch/x86/cpu/ivybridge/early_init.c @@ -14,20 +14,6 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>
-static void sandybridge_setup_lpc_bars(pci_dev_t lpc_dev) -{ - /* Setting up Southbridge. In the northbridge code. */ - debug("Setting up static southbridge registers\n"); - x86_pci_write_config32(lpc_dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1); - - x86_pci_write_config32(lpc_dev, PMBASE, DEFAULT_PMBASE | 1); - x86_pci_write_config8(lpc_dev, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ - - debug("Disabling watchdog reboot\n"); - setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ - outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ -} - static void sandybridge_setup_northbridge_bars(struct udevice *dev) { /* Set up all hardcoded northbridge BARs */ @@ -74,8 +60,6 @@ static int bd82x6x_northbridge_probe(struct udevice *dev) dm_pci_write_config8(dev, 0xf3, reg8); }
- sandybridge_setup_lpc_bars(PCH_LPC_DEV); - sandybridge_setup_northbridge_bars(dev);
/* Device Enable */ diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index dd7b788..a445b03 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -621,6 +621,18 @@ void lpc_enable(pci_dev_t dev)
static int bd82x6x_lpc_init(struct udevice *dev) { + /* Setting up Southbridge. In the northbridge code. */ + debug("Setting up static southbridge registers\n"); + dm_pci_write_config32(dev->parent, PCH_RCBA_BASE, DEFAULT_RCBA | 1); + dm_pci_write_config32(dev->parent, PMBASE, DEFAULT_PMBASE | 1); + + /* Enable ACPI BAR */ + dm_pci_write_config8(dev->parent, ACPI_CNTL, 0x80); + + debug("Disabling watchdog reboot\n"); + setbits_le32(RCB_REG(GCS), 1 >> 5); /* No reset */ + outw(1 << 11, DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + return 0; }