-----Original Message----- From: York Sun [mailto:york.sun@nxp.com] Sent: Wednesday, April 26, 2017 9:00 PM To: Priyanka Jain priyanka.jain@nxp.com; u-boot@lists.denx.de Subject: Re: [PATCH 1/2][v5] board: freescale: ls2080ardb: Update QIXIS code
On 04/25/2017 11:13 PM, Priyanka Jain wrote:
Update QIXIS related code to be executed only if CONFIG_FSL_QIXIS flag is enabled
As per board documentation, default sysclk is 100MHz. In case QIXIS code is not enabled, update default sysclk value to 100MHz
Signed-off-by: Priyanka Jain priyanka.jain@nxp.com
Changes for v4: Added changes for default sysclk as 100MHz
board/freescale/ls2080ardb/ls2080ardb.c | 21 +++++++++++++++++---- 1 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index c2aa101..10e8ea4 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -23,8 +23,10 @@ #include <asm/arch/ppa.h> #include <fsl_sec.h>
+#ifdef CONFIG_FSL_QIXIS #include "../common/qixis.h" #include "ls2080ardb_qixis.h" +#endif #include "../common/vid.h"
#define PIN_MUX_SEL_SDHC 0x00 @@ -58,12 +60,15 @@ unsigned long long get_qixis_addr(void)
int checkboard(void) { +#ifdef CONFIG_FSL_QIXIS u8 sw; +#endif char buf[15];
cpu_name(buf); printf("Board: %s-RDB, ", buf);
+#ifdef CONFIG_FSL_QIXIS sw = QIXIS_READ(arch); printf("Board Arch: V%d, ", sw >> 4); printf("Board version: %c, boot from ", (sw & 0xf) + 'A'); @@ -79,7 +84,7 @@ int checkboard(void) printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
+#endif
Without accessing to CPLD, do we still have alternative bank on QSPI?
York
Single bank QSPI flash, so no alternate bank possible.
Priyanka