ColdFire: PCI and misc updates for MCF5445x
Signed-off-by: TsiChungLiew Tsi-Chung.Liew@freescale.com --- cpu/mcf5445x/cpu_init.c | 1 - cpu/mcf5445x/pci.c | 61 +++++++++++ +------------------------------ cpu/mcf5445x/start.S | 25 ++++++----------- include/asm-m68k/immap.h | 8 +++--- include/asm-m68k/m5445x.h | 14 +++++----- include/configs/M54455EVB.h | 14 +++++---- 6 files changed, 46 insertions(+), 77 deletions(-)
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 6622eee..585216d 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -113,7 +113,6 @@ int cpu_init_r(void) #ifdef CONFIG_MCFTMR volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE); volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended; - u32 oscillator = CFG_RTC_OSCILLATOR;
rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF; rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF; diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c index 8ace536..0398469 100644 --- a/cpu/mcf5445x/pci.c +++ b/cpu/mcf5445x/pci.c @@ -46,48 +46,18 @@ int pci_##rw##_cfg_##size(struct pci_controller *hose, \ u16 cfg_type = 0; \ addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \ out_be32(hose->cfg_addr, addr); \ - __asm__ __volatile__("nop"); \ cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \ out_be32(hose->cfg_addr, addr & 0x7fffffff); \ - __asm__ __volatile__("nop"); \ return 0; \ }
PCI_OP(read, byte, u8 *, in_8, 3) PCI_OP(read, word, u16 *, in_le16, 2) +PCI_OP(read, dword, u32 *, in_le32, 0) PCI_OP(write, byte, u8, out_8, 3) PCI_OP(write, word, u16, out_le16, 2) PCI_OP(write, dword, u32, out_le32, 0)
-int pci_read_cfg_dword(struct pci_controller *hose, pci_dev_t dev, - int offset, u32 * val) -{ - u32 addr; - u32 tmpv; - u32 mask = 2; /* word access */ - /* Read lower 16 bits */ - addr = ((offset & 0xfc) | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - __asm__ __volatile__("nop"); - *val = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - __asm__ __volatile__("nop"); - - /* Read upper 16 bits */ - offset += 2; - addr = ((offset & 0xfc) | 1 | (dev) | 0x80000000); - out_be32(hose->cfg_addr, addr); - __asm__ __volatile__("nop"); - tmpv = (u32) in_le16((u16 *) (hose->cfg_data + (offset & mask))); - out_be32(hose->cfg_addr, addr & 0x7fffffff); - __asm__ __volatile__("nop"); - - /* combine results into dword value */ - *val = (tmpv << 16) | *val; - - return 0; -} - void pci_mcf5445x_init(struct pci_controller *hose) { volatile pci_t *pci = (volatile pci_t *)MMAP_PCI; @@ -95,7 +65,7 @@ void pci_mcf5445x_init(struct pci_controller *hose) volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; u32 barEn = 0;
- pciarb->acr = 0x001f001f; + pciarb->acr = 0x001F001F;
/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT, PCIREQ2, PCIGNT2 */ @@ -104,53 +74,58 @@ void pci_mcf5445x_init(struct pci_controller *hose) GPIO_PAR_PCI_GNT0 | GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 | GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0;
+ /* Assert reset bit */ + pci->gscr |= PCI_GSCR_PR; + pci->tcr1 |= PCI_TCR1_P;
/* Initiator windows */ - pci->iw0btar = CFG_PCI_MEM_PHYS; - pci->iw1btar = CFG_PCI_IO_PHYS; - pci->iw2btar = CFG_PCI_CFG_PHYS; + pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16); + pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16); + pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
pci->iwcr = PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO | PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO;
+ pci->icr = 0; + /* Enable bus master and mem access */ - pci->scr = PCI_SCR_MW | PCI_SCR_B | PCI_SCR_M; + pci->scr = PCI_SCR_B | PCI_SCR_M;
/* Cache line size and master latency */ - pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xFF); + pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8); pci->cr2 = 0;
#ifdef CFG_PCI_BAR0 pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0); pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B0E; + barEn |= PCI_TCR2_B0E; #endif #ifdef CFG_PCI_BAR1 pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1); pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B1E; + barEn |= PCI_TCR2_B1E; #endif #ifdef CFG_PCI_BAR2 pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2); pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B2E; + barEn |= PCI_TCR2_B2E; #endif #ifdef CFG_PCI_BAR3 pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3); pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B3E; + barEn |= PCI_TCR2_B3E; #endif #ifdef CFG_PCI_BAR4 pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4); pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B4E; + barEn |= PCI_TCR2_B4E; #endif #ifdef CFG_PCI_BAR5 pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5); pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN; - barEn |= PCI_TCR1_B5E; + barEn |= PCI_TCR2_B5E; #endif
pci->tcr2 = barEn; diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 423583d..d64c5af 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -279,14 +279,13 @@ icache_enable: move.l (%a1), %d1
move.l #0x00040100, %d0 /* Invalidate icache */ - or.l %d1, %d0 movec %d0, %CACR
- move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup icache */ + move.l #(CFG_SDRAM_BASE + 0x1c000), %d0 /* Setup icache */ movec %d0, %ACR2
- or.l #0x00088400, %d1 /* Enable bcache and icache */ - movec %d1, %CACR + move.l #0x04088020, %d0 /* Enable bcache and icache */ + movec %d0, %CACR
move.l #(ICACHE_STATUS), %a1 moveq #1, %d0 @@ -298,7 +297,7 @@ icache_disable: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d0
- and.l #0xFFF77BFF, %d0 + move.l #0xFFF77BFF, %d0 or.l #0x00040100, %d0 /* Setup cache mask */ movec %d0, %CACR /* Invalidate icache */ clr.l %d0 @@ -321,7 +320,7 @@ icache_invalid: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d0
- or.l #0x00040100, %d0 /* Invalidate icache */ + move.l #0x00040100, %d0 /* Invalidate icache */ movec %d0, %CACR /* Enable and invalidate cache */ rts
@@ -330,17 +329,11 @@ dcache_enable: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d1
- move.l #0x01000000, %d0 - or.l %d1, %d0 + move.l #0x01040100, %d0 movec %d0, %CACR /* Invalidate dcache */
- move.l #(CFG_SDRAM_BASE + 0xc000), %d0 - movec %d0, %ACR0 - move.l #0, %d0 - movec %d0, %ACR1 - - or.l #0x80000000, %d1 /* Enable bcache and icache */ - movec %d1, %CACR + move.l #0x80088020, %d0 /* Enable bcache and icache */ + movec %d0, %CACR
move.l #(DCACHE_STATUS), %a1 moveq #1, %d0 @@ -369,7 +362,7 @@ dcache_invalid: move.l #(CACR_STATUS), %a1 /* read CACR Status */ move.l (%a1), %d0
- or.l #0x01000000, %d0 /* Setup cache mask */ + move.l #0x81088020, %d0 /* Setup cache mask */ movec %d0, %CACR /* Enable and invalidate cache */ rts
diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h index ffb9a37..912753d 100644 --- a/include/asm-m68k/immap.h +++ b/include/asm-m68k/immap.h @@ -232,10 +232,10 @@ #define CFG_NUM_IRQS (128)
#ifdef CONFIG_PCI -#define CFG_PCI_BAR0 CFG_SDRAM_BASE -#define CFG_PCI_BAR4 CFG_SDRAM_BASE -#define CFG_PCI_TBATR0 (CFG_SDRAM_BASE) -#define CFG_PCI_TBATR4 (CFG_SDRAM_BASE) +#define CFG_PCI_BAR0 (CFG_MBAR) +#define CFG_PCI_BAR5 (CFG_SDRAM_BASE) +#define CFG_PCI_TBATR0 (CFG_MBAR) +#define CFG_PCI_TBATR5 (CFG_SDRAM_BASE) #endif #endif /* CONFIG_M54455 */
diff --git a/include/asm-m68k/m5445x.h b/include/asm-m68k/m5445x.h index f3bd229..7fcf4ef 100644 --- a/include/asm-m68k/m5445x.h +++ b/include/asm-m68k/m5445x.h @@ -1204,13 +1204,13 @@ #define PCI_TCR1_P (0x00010000) /* Prefetch reads */ #define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
-#define PCI_TCR1_B5E (0x00002000) /* */ -#define PCI_TCR1_B4E (0x00001000) /* */ -#define PCI_TCR1_B3E (0x00000800) /* */ -#define PCI_TCR1_B2E (0x00000400) /* */ -#define PCI_TCR1_B1E (0x00000200) /* */ -#define PCI_TCR1_B0E (0x00000100) /* */ -#define PCI_TCR1_CR (0x00000001) /* */ +#define PCI_TCR2_B5E (0x00002000) /* */ +#define PCI_TCR2_B4E (0x00001000) /* */ +#define PCI_TCR2_B3E (0x00000800) /* */ +#define PCI_TCR2_B2E (0x00000400) /* */ +#define PCI_TCR2_B1E (0x00000200) /* */ +#define PCI_TCR2_B0E (0x00000100) /* */ +#define PCI_TCR2_CR (0x00000001) /* */
#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20) #define PCI_TBATR_EN (0x00000001) /* Enable */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 211f11d..581c794 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -176,6 +176,10 @@ /* PCI */ #ifdef CONFIG_CMD_PCI #define CONFIG_PCI 1 +#define CONFIG_PCI_PNP 1 +#define CONFIG_SKIPPCI_HOSTBRIDGE + +#define CFG_PCI_CACHE_LINE_SIZE 4
#define CFG_PCI_MEM_BUS 0xA0000000 #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS @@ -192,9 +196,7 @@
/* FPGA - Spartan 2 */ /* experiment -#define CONFIG_FPGA -#define CONFIG_FPGA_XILINX -#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA CFG_SPARTAN3 #define CONFIG_FPGA_COUNT 1 #define CFG_FPGA_PROG_FEEDBACK #define CFG_FPGA_CHECK_CTRLC @@ -286,9 +288,9 @@ # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) # define CFG_ENV_SECT_SIZE 0x2000 #else -# define CFG_FLASH_BASE CFG_FLASH0_BASE -# define CFG_FLASH0_BASE CFG_CS1_BASE -# define CFG_FLASH1_BASE CFG_CS0_BASE +# define CFG_FLASH_BASE CFG_CS0_BASE +# define CFG_FLASH0_BASE CFG_CS0_BASE +# define CFG_FLASH1_BASE CFG_CS1_BASE # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000) # define CFG_ENV_SECT_SIZE 0x20000 #endif