On Friday 22 November 2013 02:16 AM, Vaibhav Bedia wrote:
On Thu, Nov 21, 2013 at 1:18 AM, Lokesh Vutla lokeshvutla@ti.com wrote:
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers.
This patch does too many things, some of which affects AM335x and needs to be split up. I lost track of what you were doing as i scrolled down :\
It does only two things. Update IO settings and emif configuration. I wanted to keep these things in a single patch so that if some functionality breaks down I can burn down to this patch.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com
arch/arm/cpu/armv7/am33xx/ddr.c | 147 +++++++++++++++++++- arch/arm/cpu/armv7/am33xx/emif4.c | 25 +++- arch/arm/include/asm/arch-am33xx/clocks_am33xx.h | 3 + arch/arm/include/asm/arch-am33xx/cpu.h | 5 + arch/arm/include/asm/arch-am33xx/ddr_defs.h | 33 ++++- arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 1 + arch/arm/include/asm/emif.h | 12 ++ board/isee/igep0033/board.c | 10 +- board/phytec/pcm051/board.c | 12 +- board/siemens/dxr2/board.c | 10 +- board/siemens/pxm2/board.c | 10 +- board/siemens/rut/board.c | 10 +- board/ti/am335x/board.c | 40 +++++- board/ti/am43xx/board.c | 66 +++++++++ board/ti/ti814x/evm.c | 4 +- board/ti/ti816x/evm.c | 12 +- 16 files changed, 373 insertions(+), 27 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fa697c7..fbee51d 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -36,6 +36,74 @@ static struct ddr_data_regs *ddr_data_reg[2] = { static struct ddr_cmdtctrl *ioctrl_reg = { (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
+static inline u32 get_mr(int nr, u32 cs, u32 mr_addr) +{
u32 mr;mr_addr |= cs << EMIF_REG_CS_SHIFT;writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&((mr & 0xff000000) >> 24) == (mr & 0xff))return mr & 0xff;elsereturn mr;+}
+static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val) +{
mr_addr |= cs << EMIF_REG_CS_SHIFT;writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);+}
+static void configure_mr(int nr, u32 cs) +{
u32 mr_addr;while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK);set_mr(nr, cs, LPDDR2_MR10, 0x56);set_mr(nr, cs, LPDDR2_MR1, 0x43);set_mr(nr, cs, LPDDR2_MR2, 0x2);mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;set_mr(nr, cs, mr_addr, 0x2);+}
+/*
- Configure EMIF4D5 registers and MR registers
- */
+void config_sdram_emif4d5(const struct emif_regs *regs, int nr) +{
writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);writel(regs->emif_rd_wr_lvl_rmp_win,&emif_reg[nr]->emif_rd_wr_lvl_rmp_win);writel(regs->emif_rd_wr_lvl_rmp_ctl,&emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);writel(regs->emif_rd_wr_exec_thresh,&emif_reg[nr]->emif_rd_wr_exec_thresh);clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,EMIF_REG_INITREF_DIS_MASK);writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);configure_mr(nr, 0);configure_mr(nr, 1);+}
Why can't this portion be shared with the other OMAPs? It looks to be following a recommended sequence and i can't see why that would vary.
Yes, my ultimate goal is to have a single emif file, but with the current position of emif file for OMAP's I can't reuse. This is in my To do list. I have already discussed this with Tom
Thanks Lokesh
It's just too hard to review so many changes in a single patch so i'll stop here, sorry.