Reparenting a clock C with a new parent P means that C will only continue clocking if P is already clocking when the mux is updated. In case the parent is currently disabled, failures (stalls) are likely to happen.
This is exactly what happens on i.MX8 when enabling the video pipeline. We tell LCDIF clocks to use the VIDEO PLL as input, while the VIDEO PLL is currently off. This all happens as part of the assigned-clocks handling procedure, where the reparenting happens before the enable() calls. Enabling the parents as part of the reparenting procedure seems sane and also matches the logic applied in other parts of the CCM.
Signed-off-by: Miquel Raynal miquel.raynal@bootlin.com --- drivers/clk/clk-uclass.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index ed6e60bc484..24f801e16f1 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -595,6 +595,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent) if (!ops->set_parent) return -ENOSYS;
+ ret = clk_enable(parent); + if (ret) + return ret; + ret = ops->set_parent(clk, parent); if (ret) return ret;