Add Ethernet support.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- Hi,
As far as I can see mx6qarm2 and mx6qsabresd has the same circuitry related to AR8031 Ethernet PHY.
However, with this patch I still get 25MHz instead of 125MHz in the AR8031 CLKO pin and Ethernet is not functional.
Any ideas are appreciated.
Thanks!
board/freescale/mx6qsabresd/mx6qsabresd.c | 84 +++++++++++++++++++++++++++++ include/configs/mx6qsabresd.h | 13 ++++- 2 files changed, 95 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c b/board/freescale/mx6qsabresd/mx6qsabresd.c index c86b51b..4f47fd3 100644 --- a/board/freescale/mx6qsabresd/mx6qsabresd.c +++ b/board/freescale/mx6qsabresd/mx6qsabresd.c @@ -56,6 +56,24 @@ iomux_v3_cfg_t uart1_pads[] = { MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), };
+iomux_v3_cfg_t enet_pads[] = { + MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + iomux_v3_cfg_t usdhc3_pads[] = { MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -71,6 +89,11 @@ static void setup_iomux_uart(void) imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); }
+static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[1] = { {USDHC3_BASE_ADDR}, @@ -95,9 +118,70 @@ u32 get_board_rev(void) return 0x63000; }
+ +#define MII_MMD_ACCESS_CTRL_REG 0xd +#define MII_MMD_ACCESS_ADDR_DATA_REG 0xe +#define MII_DBG_PORT_REG 0x1d +#define MII_DBG_PORT2_REG 0x1e + +int fecmxc_mii_postcall(int phy) +{ + unsigned short val; + + /* + * Due to the i.MX6Q SabreSD board HW design,there is + * no 125Mhz clock input from SOC. In order to use RGMII, + * We need enable AR8031 ouput a 125MHz clk from CLK_25M + */ + miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x7); + miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, 0x8016); + miiphy_write("FEC", phy, MII_MMD_ACCESS_CTRL_REG, 0x4007); + miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); + val &= 0xffe3; + val |= 0x18; + miiphy_write("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, val); + + /* For the RGMII phy, we need enable tx clock delay */ + miiphy_write("FEC", phy, MII_DBG_PORT_REG, 0x5); + miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); + val |= 0x0100; + miiphy_write("FEC", phy, MII_DBG_PORT2_REG, val); + + miiphy_write("FEC", phy, MII_BMCR, 0xa100); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + return ret; + } + + dev = eth_get_dev_by_name("FEC"); + if (!dev) { + printf("FEC MXC: Unable to get FEC device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXC: Unable to register FEC mii postcall\n"); + return ret; + } + + return 0; +} + int board_early_init_f(void) { setup_iomux_uart(); + setup_iomux_enet();
return 0; } diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h index 448ce28..0f8bcf6 100644 --- a/include/configs/mx6qsabresd.h +++ b/include/configs/mx6qsabresd.h @@ -33,9 +33,8 @@ #define CONFIG_REVISION_TAG
/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN CONFIG_ENV_SIZE +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
-#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_MXC_GPIO
@@ -55,6 +54,16 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 1 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1