Re: [PATCH 01/14] mips: mtmips: add support for MediaTek MT7621 SoC

Am Donnerstag, dem 04.11.2021 um 17:48 +0800 schrieb Weijie Gao:

This patch adds support for MediaTek MT7621 SoC. All files are dedicated for u-boot.

Currently only ramboot is supported. The default build target is u-boot-lzma.img. This file can be booted using bootm command, or be used as a payload of the SDK preloader of MT7621.

The specification of this chip: https://www.mediatek.com/products/homenetworking/mt7621

Signed-off-by: Weijie Gao weijie.gao@mediatek.com

arch/mips/dts/mt7621.dtsi | 372 ++++++++++++++++++++++++++ arch/mips/mach-mtmips/Kconfig | 29 +- arch/mips/mach-mtmips/Makefile | 5 + arch/mips/mach-mtmips/cpu.c | 4 + arch/mips/mach-mtmips/mt7621/Kconfig | 23 ++ arch/mips/mach-mtmips/mt7621/Makefile | 5 + arch/mips/mach-mtmips/mt7621/compat.c | 21 ++ arch/mips/mach-mtmips/mt7621/init.c | 156 +++++++++++ arch/mips/mach-mtmips/mt7621/mt7621.h | 204 ++++++++++++++ arch/mips/mach-mtmips/mt7621/serial.c | 23 ++ include/configs/mt7621.h | 41 +++ 11 files changed, 879 insertions(+), 4 deletions(-) create mode 100644 arch/mips/dts/mt7621.dtsi create mode 100644 arch/mips/mach-mtmips/mt7621/Kconfig create mode 100644 arch/mips/mach-mtmips/mt7621/Makefile create mode 100644 arch/mips/mach-mtmips/mt7621/compat.c create mode 100644 arch/mips/mach-mtmips/mt7621/init.c create mode 100644 arch/mips/mach-mtmips/mt7621/mt7621.h create mode 100644 arch/mips/mach-mtmips/mt7621/serial.c create mode 100644 include/configs/mt7621.h

diff --git a/arch/mips/dts/mt7621.dtsi b/arch/mips/dts/mt7621.dtsi new file mode 100644 index 0000000000..c09350b370 --- /dev/null +++ b/arch/mips/dts/mt7621.dtsi @@ -0,0 +1,372 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (C) 2021 MediaTek Inc. All rights reserved.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#include <dt-bindings/clock/mt7621-clk.h> +#include <dt-bindings/reset/mt7621-reset.h> +#include <dt-bindings/phy/phy.h>

+/ {

• #address-cells = <1>;
• #size-cells = <1>;
• compatible = "mediatek,mt7621-soc";
• cpus {

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• cpu@0 {
  

• 	device_type = "cpu";
  

• 	compatible = "mips,mips1004Kc";
  

• 	reg = <0>;
  

• };
  

• cpu@1 {
  

• 	device_type = "cpu";
  

• 	compatible = "mips,mips1004Kc";
  

• 	reg = <0>;
  

• };
  

• };
• clk48m: clk48m@0 {

• compatible = "fixed-clock";
  

• clock-frequency = <48000000>;
  

• #clock-cells = <0>;
  

• };
• clk50m: clk50m@0 {

• compatible = "fixed-clock";
  

• clock-frequency = <50000000>;
  

• #clock-cells = <0>;
  

• };
• sysc: sysc@1e000000 {

• compatible = "mediatek,mt7621-sysc", "syscon";
  

• reg = <0x1e000000 0x100>;
  

• };
• clkctrl: clkctrl@1e000030 {

• compatible = "mediatek,mt7621-clk";
  

• mediatek,sysc = <&sysc>;
  

• mediatek,memc = <&memc>;
  

• #clock-cells = <1>;
  

• u-boot,dm-pre-reloc;
  

• };
• rstctrl: rstctrl@1e000034 {

• compatible = "mediatek,mtmips-reset";
  

• reg = <0x1e000034 0x4>;
  

• #reset-cells = <1>;
  

• };
• reboot: resetctl-reboot {

• compatible = "resetctl-reboot";
  

• resets = <&rstctrl RST_SYS>;
  

• reset-names = "sysreset";
  

• };
• memc: memc@1e005000 {

• compatible = "mediatek,mt7621-memc", "syscon";
  

• reg = <0x1e005000 0x1000>;
  

• };
• pinctrl: pinctrl@1e000060 {

• compatible = "mediatek,mt7621-pinctrl";
  

• reg = <0x1e000048 0x30>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&state_default>;
  

• state_default: pin_state {
  

• 	uart1 {
  

• 		groups = "uart1";
  

• 		function = "uart";
  

• 	};
  

• 	gpios {
  

• 		groups = "i2c", "uart3", "pcie reset";
  

• 		function = "gpio";
  

• 	};
  

• 	jtag {
  

• 		groups = "jtag";
  

• 		function = "jtag";
  

• 	};
  

• 	wdt {
  

• 		groups = "wdt";
  

• 		function = "wdt rst";
  

• 	};
  

• };
  

• uart1_pins: uart1_pins {
  

• 	groups = "uart1";
  

• 	function = "uart";
  

• };
  

• uart2_pins: uart2_pins {
  

• 	groups = "uart2";
  

• 	function = "uart";
  

• };
  

• uart3_pins: uart3_pins {
  

• 	groups = "uart3";
  

• 	function = "uart";
  

• };
  

• sdxc_pins: sdxc_pins {
  

• 	groups = "sdxc";
  

• 	function = "sdxc";
  

• };
  

• spi_pins: spi_pins {
  

• 	groups = "spi";
  

• 	function = "spi";
  

• };
  

• eth_pins: eth_pins {
  

• 	mdio_pins {
  

• 		groups = "mdio";
  

• 		function = "mdio";
  

• 	};
  

• 	rgmii1_pins {
  

• 		groups = "rgmii1";
  

• 		function = "rgmii";
  

• 	};
  

• 	esw_pins {
  

• 		groups = "esw int";
  

• 		function = "esw int";
  

• 	};
  

• 	mdio_pconf {
  

• 		groups = "mdio";
  

• 		drive-strength = <2>;
  

• 	};
  

• };
  

• };
• watchdog: watchdog@1e000100 {

• compatible = "mediatek,mt7621-wdt";
  

• reg = <0x1e000100 0x40>;
  

• resets = <&rstctrl RST_TIMER>;
  

• reset-names = "wdt";
  

• status = "disabled";
  

• };
• gpio: gpio@1e000600 {

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• compatible = "mtk,mt7621-gpio";
  

• reg = <0x1e000600 0x100>;
  

• resets = <&rstctrl RST_PIO>;
  

• reset-names = "pio";
  

• gpio0: bank@0 {
  

• 	reg = <0>;
  

• 	compatible = "mtk,mt7621-gpio-bank";
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpio1: bank@1 {
  

• 	reg = <1>;
  

• 	compatible = "mtk,mt7621-gpio-bank";
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• gpio2: bank@2 {
  

• 	reg = <2>;
  

• 	compatible = "mtk,mt7621-gpio-bank";
  

• 	gpio-controller;
  

• 	#gpio-cells = <2>;
  

• };
  

• };
• spi: spi@1e000b00 {

• compatible = "ralink,mt7621-spi";
  

• reg = <0x1e000b00 0x40>;
  

• status = "disabled";
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&spi_pins>;
  

• resets = <&rstctrl RST_SPI>;
  

• reset-names = "spi";
  

• clocks = <&clkctrl CLK_SPI>;
  

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• };
• uart0: uart1@1e000c00 {

• compatible = "mediatek,hsuart", "ns16550a";
  

• reg = <0x1e000c00 0x100>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&uart1_pins>;
  

• clocks = <&clkctrl CLK_UART1>;
  

• resets = <&rstctrl RST_UART1>;
  

• reg-shift = <2>;
  

• };
• uart1: uart2@1e000d00 {

• compatible = "mediatek,hsuart", "ns16550a";
  

• reg = <0x1e000d00 0x100>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&uart2_pins>;
  

• clocks = <&clkctrl CLK_UART2>;
  

• resets = <&rstctrl RST_UART2>;
  

• reg-shift = <2>;
  

• status = "disabled";
  

• };
• uart2: uart3@1e000e00 {

• compatible = "mediatek,hsuart", "ns16550a";
  

• reg = <0x1e000e00 0x100>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&uart3_pins>;
  

• clocks = <&clkctrl CLK_UART3>;
  

• resets = <&rstctrl RST_UART3>;
  

• reg-shift = <2>;
  

• status = "disabled";
  

• };
• eth: eth@1e100000 {

• compatible = "mediatek,mt7621-eth";
  

• reg = <0x1e100000 0x20000>;
  

• mediatek,ethsys = <&sysc>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&eth_pins>;
  

• resets = <&rstctrl RST_FE>, <&rstctrl RST_GMAC>,
  

<&rstctrl RST_MCM>;

• reset-names = "fe", "gmac", "mcm";
  

• clocks = <&clkctrl CLK_GMAC>,
  

• 	 <&clkctrl CLK_FE>;
  

• clock-names = "gmac", "fe";
  

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• mediatek,gmac-id = <0>;
  

• phy-mode = "rgmii";
  

• mediatek,switch = "mt7530";
  

• mediatek,mcm;
  

• fixed-link {
  

• 	speed = <1000>;
  

• 	full-duplex;
  

• };
  

• };
• mmc: mmc@1e130000 {

• compatible = "mediatek,mt7621-mmc";
  

• reg = <0x1e130000 0x4000>;
  

• status = "disabled";
  

• bus-width = <4>;
  

• builtin-cd = <1>;
  

• r_smpl = <1>;
  

• pinctrl-names = "default";
  

• pinctrl-0 = <&sdxc_pins>;
  

• clocks = <&clk50m>, <&clkctrl CLK_SDXC>;
  

• clock-names = "source", "hclk";
  

• resets = <&rstctrl RST_SDXC>;
  

• };
• ssusb: usb@1e1c0000 {

• compatible = "mediatek,mt7621-xhci", "mediatek,mtk-
  

xhci";

• reg = <0x1e1c0000 0x1000>, <0x1e1d0700 0x100>;
  

• reg-names = "mac", "ippc";
  

• /* power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF1>;
  

*/

• clocks = <&clk48m>, <&clk48m>;
  

• clock-names = "sys_ck", "ref_ck";
  

• phys = <&u2port0 PHY_TYPE_USB2>,
  

•        <&u3port0 PHY_TYPE_USB3>,
  

•        <&u2port1 PHY_TYPE_USB2>;
  

• status = "disabled";
  

• };
• u3phy: usb-phy@1e1d0000 {

• compatible = "mediatek,mt7621-u3phy",
  

• 	     "mediatek,generic-tphy-v1";
  

• reg = <0x1e1d0000 0x700>;
  

• #address-cells = <1>;
  

• #size-cells = <1>;
  

• ranges;
  

• status = "disabled";
  

• u2port0: usb-phy@1e1d0800 {
  

• 	reg = <0x1e1d0800 0x0100>;
  

• 	#phy-cells = <1>;
  

• 	clocks = <&clk48m>;
  

• 	clock-names = "ref";
  

• };
  

• u3port0: usb-phy@1e1d0900 {
  

• 	reg = <0x1e1d0900 0x0100>;
  

• 	#phy-cells = <1>;
  

• };
  

• u2port1: usb-phy@1e1d1000 {
  

• 	reg = <0x1e1d1000 0x0100>;
  

• 	#phy-cells = <1>;
  

• 	clocks = <&clk48m>;
  

• 	clock-names = "ref";
  

• };
  

• };
• i2c: i2c@1e000900 {

• compatible = "i2c-gpio";
  

• status = "disabled";
  

• i2c-gpio,delay-us = <3>;
  

• gpios = <&gpio0 3 1>, /* PIN3 as SDA */
  

• 	<&gpio0 4 1>; /* PIN4 as CLK */
  

• #address-cells = <1>;
  

• #size-cells = <0>;
  

• };

+}; diff --git a/arch/mips/mach-mtmips/Kconfig b/arch/mips/mach- mtmips/Kconfig index 151b004603..9b30535411 100644 --- a/arch/mips/mach-mtmips/Kconfig +++ b/arch/mips/mach-mtmips/Kconfig @@ -9,6 +9,7 @@ config SYS_MALLOC_F_LEN

config SYS_SOC default "mt7620" if SOC_MT7620

• default "mt7621" if SOC_MT7621 default "mt7628" if SOC_MT7628

config SYS_DCACHE_SIZE @@ -18,22 +19,28 @@ config SYS_DCACHE_LINE_SIZE default 32

config SYS_ICACHE_SIZE

• default 65536

• default 65536 if SOC_MT7620 || SOC_MT7628
• default 32768 if SOC_MT7621

config SYS_ICACHE_LINE_SIZE default 32

config SYS_TEXT_BASE

• default 0x9c000000 if !SPL
• default 0x80200000 if SPL

• default 0x9c000000 if !SPL && !SOC_MT7621
• default 0x80200000 if SPL || SOC_MT7621

config SPL_TEXT_BASE

• default 0x9c000000

• default 0x9c000000 if !SOC_MT7621
• default 0x80100000 if SOC_MT7621

+config TPL_TEXT_BASE

• default 0xbfc00000 if SOC_MT7621

config SPL_PAYLOAD default "u-boot-lzma.img" if SPL_LZMA

config BUILD_TARGET

• default "u-boot-lzma.img" if SOC_MT7621 # Only ramboot is

supported now default "u-boot-with-spl.bin" if SPL default "u-boot.bin"

@@ -55,6 +62,19 @@ config SOC_MT7620 help This supports MediaTek MT7620.

+config SOC_MT7621

• bool "MT7621"
• select MIPS_CM
• select MIPS_L2_CACHE
• select SYS_CACHE_SHIFT_5
• select SYS_MIPS_CACHE_INIT_RAM_LOAD
• select PINCTRL_MT7621
• select MTK_SERIAL
• select REGMAP
• select SYSCON
• help

•  This supports MediaTek MT7621.
  

config SOC_MT7628 bool "MT7628" select SYS_CACHE_SHIFT_5 @@ -80,6 +100,7 @@ config SOC_MT7628 endchoice

source "arch/mips/mach-mtmips/mt7620/Kconfig" +source "arch/mips/mach-mtmips/mt7621/Kconfig" source "arch/mips/mach-mtmips/mt7628/Kconfig"

endmenu diff --git a/arch/mips/mach-mtmips/Makefile b/arch/mips/mach- mtmips/Makefile index 4909b47ef2..9ab882dee0 100644 --- a/arch/mips/mach-mtmips/Makefile +++ b/arch/mips/mach-mtmips/Makefile @@ -1,9 +1,14 @@ # SPDX-License-Identifier: GPL-2.0+

obj-y += cpu.o

+ifneq ($(CONFIG_SOC_MT7621),y) obj-y += ddr_init.o obj-y += ddr_cal.o +endif

obj-$(CONFIG_SPL_BUILD) += spl.o

obj-$(CONFIG_SOC_MT7620) += mt7620/ +obj-$(CONFIG_SOC_MT7621) += mt7621/ obj-$(CONFIG_SOC_MT7628) += mt7628/ diff --git a/arch/mips/mach-mtmips/cpu.c b/arch/mips/mach- mtmips/cpu.c index a4b5cff61d..6ca5655d46 100644 --- a/arch/mips/mach-mtmips/cpu.c +++ b/arch/mips/mach-mtmips/cpu.c @@ -16,7 +16,11 @@ DECLARE_GLOBAL_DATA_PTR;

int dram_init(void) { +#ifdef CONFIG_SOC_MT7621

• gd->ram_size = get_ram_size((void *)KSEG1, SZ_512M);

+#else gd->ram_size = get_ram_size((void *)KSEG1, SZ_256M); +#endif

to avoid cluttering the code with new ifdefs the RAM size should be a Kconfig option which default value depends on CONFIG_SOC_MTxxxx

return 0; } diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach- mtmips/mt7621/Kconfig new file mode 100644 index 0000000000..6948bee31b --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/Kconfig @@ -0,0 +1,23 @@

+if SOC_MT7621

+config DEBUG_UART_BOARD_INIT

• default y

+choice

• prompt "Board select"

+endchoice

+config SYS_CONFIG_NAME

• string "Board configuration name"
• default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB

+config SYS_BOARD

• string "Board name"
• default "mt7621" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB

+config SYS_VENDOR

• default "mediatek" if BOARD_MT7621_RFB || BOARD_MT7621_NAND_RFB

+endif diff --git a/arch/mips/mach-mtmips/mt7621/Makefile b/arch/mips/mach- mtmips/mt7621/Makefile new file mode 100644 index 0000000000..adb48ffe37 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0

+obj-y += init.o +obj-y += serial.o +obj-y += compat.o diff --git a/arch/mips/mach-mtmips/mt7621/compat.c b/arch/mips/mach- mtmips/mt7621/compat.c new file mode 100644 index 0000000000..ae2dd263f7 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/compat.c @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (C) 2021 MediaTek Inc. All rights reserved.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#include <malloc.h> +#include <asm/io.h> +#include <asm/addrspace.h>

+/* This is used for the mtk-eth driver */ +phys_addr_t noncached_alloc(size_t size, size_t align) +{

• void *ptr = memalign(align, ALIGN(size, align));
• if (!ptr)

• return 0;
  

• return KSEG1ADDR((ulong)ptr);

+} diff --git a/arch/mips/mach-mtmips/mt7621/init.c b/arch/mips/mach- mtmips/mt7621/init.c new file mode 100644 index 0000000000..ca72d37980 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/init.c @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#include <clk.h> +#include <dm.h> +#include <dm/uclass.h> +#include <dt-bindings/clock/mt7621-clk.h> +#include <asm/global_data.h> +#include <linux/io.h> +#include "mt7621.h"

+DECLARE_GLOBAL_DATA_PTR;

+static const char *const boot_mode[(CHIP_MODE_M >> CHIP_MODE_S) + 1] = {

• [1] = "NAND 2K+64",
• [2] = "SPI-NOR 3-Byte Addr",
• [3] = "SPI-NOR 4-Byte Addr",
• [10] = "NAND 2K+128",
• [11] = "NAND 4K+128",
• [12] = "NAND 4K+256",

+};

+int print_cpuinfo(void) +{

• void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
• u32 cpu_clk, ddr_clk, bus_clk, xtal_clk, timer_freq;
• u32 val, ver, eco, pkg, core, dram, chipmode;
• struct udevice *clkdev;
• const char *bootdev;
• struct clk clk;
• int ret;
• val = readl(sysc + SYSCTL_CHIP_REV_ID_REG);
• ver = (val & VER_ID_M) >> VER_ID_S;
• eco = (val & ECO_ID_M) >> ECO_ID_S;
• pkg = !!(val & PKG_ID);
• core = !!(val & CPU_ID);
• val = readl(sysc + SYSCTL_SYSCFG0_REG);
• dram = val & DRAM_TYPE;
• chipmode = (val & CHIP_MODE_M) >> CHIP_MODE_S;
• bootdev = boot_mode[chipmode];
• if (!bootdev)

• bootdev = "Unsupported boot mode";
  

• printf("CPU: MediaTek MT7621%c ver %u, eco %u\n",

•       core ? (pkg ? 'A' : 'N') : 'S', ver, eco);
  

• printf("Boot: DDR%u, %s\n", dram ? 2 : 3, bootdev);
• ret = uclass_get_device_by_driver(UCLASS_CLK,

DM_DRIVER_GET(mt7621_clk),

• 			  &clkdev);
  

• if (ret)

• return ret;
  

• clk.dev = clkdev;
• clk.id = CLK_CPU;
• cpu_clk = clk_get_rate(&clk);
• clk.id = CLK_SYS;
• bus_clk = clk_get_rate(&clk);
• clk.id = CLK_DDR;
• ddr_clk = clk_get_rate(&clk);
• clk.id = CLK_XTAL;
• xtal_clk = clk_get_rate(&clk);
• clk.id = CLK_MIPS_CNT;
• timer_freq = clk_get_rate(&clk);
• /* Set final timer frequency */
• if (timer_freq)

• gd->arch.timer_freq = timer_freq;
  

• printf("Clock: CPU: %uMHz, DDR: %uMT/s, Bus: %uMHz, XTAL:

%uMHz\n",

•       cpu_clk / 1000000, ddr_clk / 500000, bus_clk / 1000000,
  

•       xtal_clk / 1000000);
  

• return 0;

+}

+void lowlevel_init(void) +{

• void __iomem *usbh = ioremap_nocache(SSUSB_BASE, SSUSB_SIZE);
• /* Setup USB xHCI */
• writel((0x20 << SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_S) |

•       (0x20 << SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_S) |
  

•       (2 << SSUSB_MAC3_SYS_CK_GATE_MODE_S) |
  

•       (2 << SSUSB_MAC2_SYS_CK_GATE_MODE_S) | 0x10,
  

•       usbh + SSUSB_MAC_CK_CTRL_REG);
  

• writel((2 << SSUSB_PLL_PREDIV_PE1D_S) | (1 <<

SSUSB_PLL_PREDIV_U3_S) |

•       (4 << SSUSB_PLL_FBKDI_S), usbh +
  

DA_SSUSB_U3PHYA_10_REG);

• writel((0x18 << SSUSB_PLL_FBKDIV_PE2H_S) |

•       (0x18 << SSUSB_PLL_FBKDIV_PE1D_S) |
  

•       (0x18 << SSUSB_PLL_FBKDIV_PE1H_S) |
  

•       (0x1e << SSUSB_PLL_FBKDIV_U3_S),
  

•       usbh + DA_SSUSB_PLL_FBKDIV_REG);
  

• writel((0x1e400000 << SSUSB_PLL_PCW_NCPO_U3_S),

•       usbh + DA_SSUSB_PLL_PCW_NCPO_REG);
  

• writel((0x25 << SSUSB_PLL_SSC_DELTA1_PE1H_S) |

•       (0x73 << SSUSB_PLL_SSC_DELTA1_U3_S),
  

•       usbh + DA_SSUSB_PLL_SSC_DELTA1_REG);
  

• writel((0x71 << SSUSB_PLL_SSC_DELTA_U3_S) |

•       (0x4a << SSUSB_PLL_SSC_DELTA1_PE2D_S),
  

•       usbh + DA_SSUSB_U3PHYA_21_REG);
  

• writel((0x140 << SSUSB_PLL_SSC_PRD_S), usbh +

SSUSB_U3PHYA_9_REG);

• writel((0x11c00000 << SSUSB_SYSPLL_PCW_NCPO_S),

•       usbh + SSUSB_U3PHYA_3_REG);
  

• writel((4 << SSUSB_PCIE_CLKDRV_AMP_S) | (1 <<

SSUSB_SYSPLL_FBSEL_S) |

•       (1 << SSUSB_SYSPLL_PREDIV_S), usbh +
  

SSUSB_U3PHYA_1_REG);

• writel((0x12 << SSUSB_SYSPLL_FBDIV_S) |

SSUSB_SYSPLL_VCO_DIV_SEL |

•       SSUSB_SYSPLL_FPEN | SSUSB_SYSPLL_MONCK_EN |
  

SSUSB_SYSPLL_VOD_EN,

•       usbh + SSUSB_U3PHYA_2_REG);
  

• writel(SSUSB_EQ_CURSEL | (8 << SSUSB_RX_DAC_MUX_S) |

•       (1 << SSUSB_PCIE_SIGDET_VTH_S) | (1 <<
  

SSUSB_PCIE_SIGDET_LPF_S),

•       usbh + SSUSB_U3PHYA_11_REG);
  

• writel((0x1ff << SSUSB_RING_OSC_CNTEND_S) |

•       (0x7f << SSUSB_XTAL_OSC_CNTEND_S) |
  

SSUSB_RING_BYPASS_DET,

•       usbh + SSUSB_B2_ROSC_0_REG);
  

• writel((3 << SSUSB_RING_OSC_FRC_RECAL_S) |

SSUSB_RING_OSC_FRC_SEL,

•       usbh + SSUSB_B2_ROSC_1_REG);
  

+}

+ulong notrace get_tbclk(void) +{

• return gd->arch.timer_freq;

+}

+void _machine_restart(void) +{

• void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);
• while (1)

• writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG);
  

+} diff --git a/arch/mips/mach-mtmips/mt7621/mt7621.h b/arch/mips/mach- mtmips/mt7621/mt7621.h new file mode 100644 index 0000000000..012f5a3557 --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/mt7621.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#ifndef _MT7621_H_ +#define _MT7621_H_

+#define SYSCTL_BASE 0x1e000000 +#define SYSCTL_SIZE 0x100 +#define TIMER_BASE 0x1e000100 +#define TIMER_SIZE 0x100 +#define RBUS_BASE 0x1e000400 +#define RBUS_SIZE 0x100 +#define GPIO_BASE 0x1e000600 +#define GPIO_SIZE 0x100 +#define DMA_CFG_ARB_BASE 0x1e000800 +#define DMA_CFG_ARB_SIZE 0x100 +#define SPI_BASE 0x1e000b00 +#define SPI_SIZE 0x100 +#define UART1_BASE 0x1e000c00 +#define UART1_SIZE 0x100 +#define NFI_BASE 0x1e003000 +#define NFI_SIZE 0x800 +#define NFI_ECC_BASE 0x1e003800 +#define NFI_ECC_SIZE 0x800 +#define DRAMC_BASE 0x1e005000 +#define DRAMC_SIZE 0x1000 +#define FE_BASE 0x1e100000 +#define FE_SIZE 0xe000 +#define GMAC_BASE 0x1e110000 +#define GMAC_SIZE 0x8000 +#define SSUSB_BASE 0x1e1c0000 +#define SSUSB_SIZE 0x40000

• /* GIC Base Address */

+#define MIPS_GIC_BASE 0x1fbc0000

• /* CPC Base Address */

+#define MIPS_CPC_BASE 0x1fbf0000

• /* Flash Memory-mapped Base Address */

+#define FLASH_MMAP_BASE 0x1fc00000

+/* SRAM */ +#define FE_SRAM_BASE1 0x8000 +#define FE_SRAM_BASE2 0xa000

+/* SYSCTL_BASE */ +#define SYSCTL_CHIP_REV_ID_REG 0x0c +#define CPU_ID 0x20000 +#define PKG_ID 0x10000 +#define VER_ID_S 8 +#define VER_ID_M 0xf00 +#define ECO_ID_S 0 +#define ECO_ID_M 0x0f

+#define SYSCTL_SYSCFG0_REG 0x10 +#define XTAL_MODE_SEL_S 6 +#define XTAL_MODE_SEL_M 0x1c0 +#define DRAM_TYPE 0x10 +#define CHIP_MODE_S 0 +#define CHIP_MODE_M 0x0f

+#define BOOT_SRAM_BASE_REG 0x20

+#define SYSCTL_CLKCFG0_REG 0x2c +#define CPU_CLK_SEL_S 30 +#define CPU_CLK_SEL_M 0xc0000000 +#define MPLL_CFG_SEL_S 23 +#define MPLL_CFG_SEL_M 0x800000

+#define SYSCTL_RSTCTL_REG 0x34 +#define SYS_RST 0x01

+#define SYSCTL_CUR_CLK_STS_REG 0x44 +#define CUR_CPU_FDIV_S 8 +#define CUR_CPU_FDIV_M 0x1f00 +#define CUR_CPU_FFRAC_S 0 +#define CUR_CPU_FFRAC_M 0x1f

+#define SYSCTL_GPIOMODE_REG 0x60 +#define UART2_MODE_S 5 +#define UART2_MODE_M 0x60 +#define UART3_MODE_S 3 +#define UART3_MODE_M 0x18 +#define UART1_MODE 0x02

+/* RBUS_BASE */ +#define RBUS_DYN_CFG0_REG 0x0010 +#define CPU_FDIV_S 8 +#define CPU_FDIV_M 0x1f00 +#define CPU_FFRAC_S 0 +#define CPU_FFRAC_M 0x1f

+/* DMA_CFG_ARB_BASE */ +#define DMA_ROUTE_REG 0x000c

+/* SPI_BASE */ +#define SPI_SPACE_REG 0x003c +#define FS_SLAVE_SEL_S 12 +#define FS_SLAVE_SEL_M 0x70000 +#define FS_CLK_SEL_S 0 +#define FS_CLK_SEL_M 0xfff

+/* FE_BASE */ +#define FE_RST_GLO_REG 0x0004 +#define FE_PSE_RAM 0x04 +#define FE_PSE_MEM_EN 0x02 +#define FE_PSE_RESET 0x01

+/* SSUSB_BASE */ +#define SSUSB_MAC_CK_CTRL_REG 0x10784 +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_S 16 +#define SSUSB_MAC3_SYS_CK_GATE_MASK_TIME_M 0xff0000 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_S 8 +#define SSUSB_MAC2_SYS_CK_GATE_MASK_TIME_M 0xff00 +#define SSUSB_MAC3_SYS_CK_GATE_MODE_S 2 +#define SSUSB_MAC3_SYS_CK_GATE_MODE_M 0x0c +#define SSUSB_MAC2_SYS_CK_GATE_MODE_S 0 +#define SSUSB_MAC2_SYS_CK_GATE_MODE_M 0x03

+#define SSUSB_B2_ROSC_0_REG 0x10a40 +#define SSUSB_RING_OSC_CNTEND_S 23 +#define SSUSB_RING_OSC_CNTEND_M 0xff800000 +#define SSUSB_XTAL_OSC_CNTEND_S 16 +#define SSUSB_XTAL_OSC_CNTEND_M 0x7f0000 +#define SSUSB_RING_BYPASS_DET 0x01

+#define SSUSB_B2_ROSC_1_REG 0x10a44 +#define SSUSB_RING_OSC_FRC_RECAL_S 17 +#define SSUSB_RING_OSC_FRC_RECAL_M 0x60000 +#define SSUSB_RING_OSC_FRC_SEL 0x01

+#define SSUSB_U3PHYA_1_REG 0x10b04 +#define SSUSB_PCIE_CLKDRV_AMP_S 27 +#define SSUSB_PCIE_CLKDRV_AMP_M 0x38000000 +#define SSUSB_SYSPLL_FBSEL_S 2 +#define SSUSB_SYSPLL_FBSEL_M 0x0c +#define SSUSB_SYSPLL_PREDIV_S 0 +#define SSUSB_SYSPLL_PREDIV_M 0x03

+#define SSUSB_U3PHYA_2_REG 0x10b08 +#define SSUSB_SYSPLL_FBDIV_S 24 +#define SSUSB_SYSPLL_FBDIV_M 0x7f000000 +#define SSUSB_SYSPLL_VCO_DIV_SEL 0x200000 +#define SSUSB_SYSPLL_FPEN 0x2000 +#define SSUSB_SYSPLL_MONCK_EN 0x1000 +#define SSUSB_SYSPLL_VOD_EN 0x200

+#define SSUSB_U3PHYA_3_REG 0x10b10 +#define SSUSB_SYSPLL_PCW_NCPO_S 1 +#define SSUSB_SYSPLL_PCW_NCPO_M 0xfffffffe

+#define SSUSB_U3PHYA_9_REG 0x10b24 +#define SSUSB_PLL_SSC_PRD_S 0 +#define SSUSB_PLL_SSC_PRD_M 0xffff

+#define SSUSB_U3PHYA_11_REG 0x10b2c +#define SSUSB_EQ_CURSEL 0x1000000 +#define SSUSB_RX_DAC_MUX_S 19 +#define SSUSB_RX_DAC_MUX_M 0xf80000 +#define SSUSB_PCIE_SIGDET_VTH_S 5 +#define SSUSB_PCIE_SIGDET_VTH_M 0x60 +#define SSUSB_PCIE_SIGDET_LPF_S 3 +#define SSUSB_PCIE_SIGDET_LPF_M 0x18

+#define DA_SSUSB_PLL_FBKDIV_REG 0x10c1c +#define SSUSB_PLL_FBKDIV_PE2H_S 24 +#define SSUSB_PLL_FBKDIV_PE2H_M 0x7f000000 +#define SSUSB_PLL_FBKDIV_PE1D_S 16 +#define SSUSB_PLL_FBKDIV_PE1D_M 0x7f0000 +#define SSUSB_PLL_FBKDIV_PE1H_S 8 +#define SSUSB_PLL_FBKDIV_PE1H_M 0x7f00 +#define SSUSB_PLL_FBKDIV_U3_S 0 +#define SSUSB_PLL_FBKDIV_U3_M 0x7f

+#define DA_SSUSB_U3PHYA_10_REG 0x10c20 +#define SSUSB_PLL_PREDIV_PE1D_S 18 +#define SSUSB_PLL_PREDIV_PE1D_M 0xc0000 +#define SSUSB_PLL_PREDIV_U3_S 8 +#define SSUSB_PLL_PREDIV_U3_M 0x300 +#define SSUSB_PLL_FBKDI_S 0 +#define SSUSB_PLL_FBKDI_M 0x07

+#define DA_SSUSB_PLL_PCW_NCPO_REG 0x10c24 +#define SSUSB_PLL_PCW_NCPO_U3_S 0 +#define SSUSB_PLL_PCW_NCPO_U3_M 0x7fffffff

+#define DA_SSUSB_PLL_SSC_DELTA1_REG 0x10c38 +#define SSUSB_PLL_SSC_DELTA1_PE1H_S 16 +#define SSUSB_PLL_SSC_DELTA1_PE1H_M 0xffff0000 +#define SSUSB_PLL_SSC_DELTA1_U3_S 0 +#define SSUSB_PLL_SSC_DELTA1_U3_M 0xffff

+#define DA_SSUSB_U3PHYA_21_REG 0x10c40 +#define SSUSB_PLL_SSC_DELTA_U3_S 16 +#define SSUSB_PLL_SSC_DELTA_U3_M 0xffff0000 +#define SSUSB_PLL_SSC_DELTA1_PE2D_S 0 +#define SSUSB_PLL_SSC_DELTA1_PE2D_M 0xffff

+#endif /* _MT7621_H_ */ diff --git a/arch/mips/mach-mtmips/mt7621/serial.c b/arch/mips/mach- mtmips/mt7621/serial.c new file mode 100644 index 0000000000..393188abce --- /dev/null +++ b/arch/mips/mach-mtmips/mt7621/serial.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Copyright (C) 2020 MediaTek Inc.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#include <asm/io.h> +#include <asm/addrspace.h> +#include "mt7621.h"

+void board_debug_uart_init(void) +{

• void __iomem *base = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE);

+#if CONFIG_DEBUG_UART_BASE == 0xbe000c00 /* KSEG1ADDR(UART1_BASE) */

• clrbits_32(base + SYSCTL_GPIOMODE_REG, UART1_MODE);

+#elif CONFIG_DEBUG_UART_BASE == 0xbe000d00 /* KSEG1ADDR(UART2_BASE) */

• clrbits_32(base + SYSCTL_GPIOMODE_REG, UART2_MODE_M);

+#elif CONFIG_DEBUG_UART_BASE == 0xbe000e00 /* KSEG1ADDR(UART3_BASE) */

• clrbits_32(base + SYSCTL_GPIOMODE_REG, UART3_MODE_M);

+#endif +} diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h new file mode 100644 index 0000000000..47f7e51a1a --- /dev/null +++ b/include/configs/mt7621.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • Copyright (C) 2021 MediaTek Inc. All Rights Reserved.
• • Author: Weijie Gao weijie.gao@mediatek.com
• */

+#ifndef __CONFIG_MT7621_H +#define __CONFIG_MT7621_H

+#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_MIPS_TIMER_FREQ 440000000

+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE

+#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000

+#define CONFIG_SYS_SDRAM_BASE 0x80000000

+#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED 0x1c000000

+#define CONFIG_SYS_INIT_SP_OFFSET 0x10000

+#define CONFIG_SYS_BOOTM_LEN 0x2000000

+#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_CBSIZE 1024

+/* MMC */ +#define MMC_SUPPORTS_TUNING

+/* NAND */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1

+/* Network */ +#define CONFIG_IPADDR 192.168.1.1 +#define CONFIG_SERVERIP 192.168.1.2 +#define CONFIG_NETMASK 255.255.255.0

the default config shouldn't have any network config

+#endif /* __CONFIG_MT7621_H */