Tom,
we have additional fixes ready for you: * the TPL-build process for the Vyasa board was fixed by Jagan (by providing the correct TEXT_BASE) * a regression on Ethernet for the RK3399 and RK3368 has been resolved by adding support for its clocks * a regression on PMIC probing on the RK399 has been resolved by adding support for the assigned-clocks of the PMUCRU
Travis report is at https://travis-ci.org/ptomsich/u-boot-rockchip/builds/345699336
Thanks, Philipp.
The following changes since commit 0bb430c8494e26e8d258cf6957cdd39d2ce4f309:
Merge git://git.denx.de/u-boot-video (2018-02-24 08:02:17 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-rockchip.git master
for you to fetch changes up to 434d5a00a4578f826e7e2cef29bf2388dd760a88:
rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL (2018-02-24 18:50:03 +0100)
---------------------------------------------------------------- Jagan Teki (2): rockchip: rk3288: Add TPL_LDSCRIPT rockchip: rk3288: Fix wrong TPL_TEXT_BASE
Philipp Tomsich (3): rockchip: clk: rk3399: handle clk_enable requests for GMAC rockchip: clk: rk3368: handle clk_enable requests for GMAC rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL
arch/arm/mach-rockchip/Kconfig | 10 ++++++++++ arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds | 10 ++++++++++ configs/vyasa-rk3288_defconfig | 1 - drivers/clk/rockchip/clk_rk3368.c | 19 +++++++++++++++++++ drivers/clk/rockchip/clk_rk3399.c | 19 +++++++++++++++++++ 5 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3288/u-boot-tpl.lds