Re: [U-Boot] [PATCH v1 7/9] sunxi: mmc support

Hi Ian,

On Mar 14, 2014, at 12:33 PM, Ian Campbell wrote:

Based linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in ldscripts" vs v2014.01.

As well as the following signed-off-by the sunxi branch shows commits to these files authored by the following: Stefan Roese Tom Cubie yemao

Signed-off-by: Henrik Nordstrom henrik@henriknordstrom.net Signed-off-by: Luke Leighton lkcl@lkcl.net Signed-off-by: Oliver Schinagl oliver@schinagl.nl Signed-off-by: Wills Wang wills.wang.open@gmail.com Signed-off-by: Ian Campbell ijc@hellion.org.uk

---

arch/arm/include/asm/arch-sunxi/mmc.h | 66 ++++ board/sunxi/board.c | 13 + drivers/mmc/Makefile | 1 + drivers/mmc/sunxi_mmc.c | 650 ++++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 11 + 5 files changed, 741 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h create mode 100755 drivers/mmc/sunxi_mmc.c

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 0000000..639a7fc --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,66 @@ +/*

• • (C) Copyright 2007-2011
• • Allwinner Technology Co., Ltd. <www.allwinnertech.com>
• • Aaron leafy.myeh@allwinnertech.com
• • MMC register definition for allwinner sunxi platform.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H

+#include <linux/types.h>

+struct sunxi_mmc {

• u32 gctrl; /* (0x00) SMC Global Control Register */
• u32 clkcr; /* (0x04) SMC Clock Control Register */
• u32 timeout; /* (0x08) SMC Time Out Register */
• u32 width; /* (0x0c) SMC Bus Width Register */
• u32 blksz; /* (0x10) SMC Block Size Register */
• u32 bytecnt; /* (0x14) SMC Byte Count Register */
• u32 cmd; /* (0x18) SMC Command Register */
• u32 arg; /* (0x1c) SMC Argument Register */
• u32 resp0; /* (0x20) SMC Response Register 0 */
• u32 resp1; /* (0x24) SMC Response Register 1 */
• u32 resp2; /* (0x28) SMC Response Register 2 */
• u32 resp3; /* (0x2c) SMC Response Register 3 */
• u32 imask; /* (0x30) SMC Interrupt Mask Register */
• u32 mint; /* (0x34) SMC Masked Interrupt Status Reg */
• u32 rint; /* (0x38) SMC Raw Interrupt Status Register */
• u32 status; /* (0x3c) SMC Status Register */
• u32 ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Reg */
• u32 funcsel; /* (0x44) SMC Function Select Register */
• u32 cbcr; /* (0x48) SMC CIU Byte Count Register */
• u32 bbcr; /* (0x4c) SMC BIU Byte Count Register */
• u32 dbgc; /* (0x50) SMC Debug Enable Register */
• u32 res0[11]; /* (0x54~0x7c) */
• u32 dmac; /* (0x80) SMC IDMAC Control Register */
• u32 dlba; /* (0x84) SMC IDMAC Descr List Base Addr Reg */
• u32 idst; /* (0x88) SMC IDMAC Status Register */
• u32 idie; /* (0x8c) SMC IDMAC Interrupt Enable Register */
• u32 chda; /* (0x90) */
• u32 cbda; /* (0x94) */
• u32 res1[26]; /* (0x98~0xff) */
• u32 fifo; /* (0x100) SMC FIFO Access Address */

+};

+int sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index bffef4f..5dbcf2a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -30,6 +30,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/mmc.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -59,6 +60,18 @@ int dram_init(void) return 0; }

+#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{

• sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);

+#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA)

• sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);

+#endif

• return 0;

+} +#endif

#ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index e793ed9..c695841 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o ifdef CONFIG_SPL_BUILD diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100755 index 0000000..13eba76 --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,650 @@ +/*

• • (C) Copyright 2007-2011
• • Allwinner Technology Co., Ltd. <www.allwinnertech.com>
• • Aaron leafy.myeh@allwinnertech.com
• • MMC driver for allwinner sunxi platform.
• • See file CREDITS for list of people who contributed to this
• • project.
• • This program is free software; you can redistribute it and/or
• • modify it under the terms of the GNU General Public License as
• • published by the Free Software Foundation; either version 2 of
• • the License, or (at your option) any later version.
• • This program is distributed in the hope that it will be useful,
• • but WITHOUT ANY WARRANTY; without even the implied warranty of
• • MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
• • GNU General Public License for more details.
• • You should have received a copy of the GNU General Public License
• • along with this program; if not, write to the Free Software
• • Foundation, Inc., 59 Temple Place, Suite 330, Boston,
• • MA 02111-1307 USA
• */

+#include <common.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h>

+static void dumphex32(char *name, char *base, int len) +{

• __u32 i;
• debug("dump %s registers:", name);
• for (i = 0; i < len; i += 4) {

• if (!(i & 0xf))
  

• 	debug("\n0x%p : ", base + i);
  

• debug("0x%08x ", readl(base + i));
  

• }
• debug("\n");

+}

+static void dumpmmcreg(struct sunxi_mmc *reg) +{

• debug("dump mmc registers:\n");
• debug("gctrl 0x%08x\n", reg->gctrl);
• debug("clkcr 0x%08x\n", reg->clkcr);
• debug("timeout 0x%08x\n", reg->timeout);
• debug("width 0x%08x\n", reg->width);
• debug("blksz 0x%08x\n", reg->blksz);
• debug("bytecnt 0x%08x\n", reg->bytecnt);
• debug("cmd 0x%08x\n", reg->cmd);
• debug("arg 0x%08x\n", reg->arg);
• debug("resp0 0x%08x\n", reg->resp0);
• debug("resp1 0x%08x\n", reg->resp1);
• debug("resp2 0x%08x\n", reg->resp2);
• debug("resp3 0x%08x\n", reg->resp3);
• debug("imask 0x%08x\n", reg->imask);
• debug("mint 0x%08x\n", reg->mint);
• debug("rint 0x%08x\n", reg->rint);
• debug("status 0x%08x\n", reg->status);
• debug("ftrglevel 0x%08x\n", reg->ftrglevel);
• debug("funcsel 0x%08x\n", reg->funcsel);
• debug("dmac 0x%08x\n", reg->dmac);
• debug("dlba 0x%08x\n", reg->dlba);
• debug("idst 0x%08x\n", reg->idst);
• debug("idie 0x%08x\n", reg->idie);

+}

^^^ #ifdef DEBUG here?

+struct sunxi_mmc_des {

• u32 reserved1_1:1;
• u32 dic:1; /* disable interrupt on completion */
• u32 last_des:1; /* 1-this data buffer is the last buffer */
• u32 first_des:1; /* 1-data buffer is the first buffer,

• 		   0-data buffer contained in the next
  

• 		   descriptor is 1st buffer */
  

• u32 des_chain:1; /* 1-the 2nd address in the descriptor is the

• 		   next descriptor address */
  

• u32 end_of_ring:1; /* 1-last descriptor flag when using dual

• 		   data buffer in descriptor */
  

• u32 reserved1_2:24;
• u32 card_err_sum:1; /* transfer error flag */
• u32 own:1; /* des owner:1-idma owns it, 0-host owns it */

+#define SDXC_DES_NUM_SHIFT 16 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT)

• u32 data_buf1_sz:16;
• u32 data_buf2_sz:16;
• u32 buf_addr_ptr1;
• u32 buf_addr_ptr2;

+};

+struct sunxi_mmc_host {

• unsigned mmc_no;
• uint32_t *mclkreg;
• unsigned database;
• unsigned fatal_err;
• unsigned mod_clk;
• struct sunxi_mmc *reg;

+};

+/* support 4 mmc hosts */ +struct mmc mmc_dev[4]; +struct sunxi_mmc_host mmc_host[4];

^ hosts & mmc structs can be allocated even for SPL now

+static int mmc_resource_init(int sdc_no) +{

• struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
• struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
• debug("init mmc %d resource\n", sdc_no);
• switch (sdc_no) {
• case 0:

• mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE;
  

• mmchost->mclkreg = &ccm->sd0_clk_cfg;
  

• break;
  

• case 1:

• mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE;
  

• mmchost->mclkreg = &ccm->sd1_clk_cfg;
  

• break;
  

• case 2:

• mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE;
  

• mmchost->mclkreg = &ccm->sd2_clk_cfg;
  

• break;
  

• case 3:

• mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE;
  

• mmchost->mclkreg = &ccm->sd3_clk_cfg;
  

• break;
  

• default:

• printf("Wrong mmc number %d\n", sdc_no);
  

• return -1;
  

• }
• mmchost->database = (unsigned int)mmchost->reg + 0x100;
• mmchost->mmc_no = sdc_no;
• return 0;

+}

+static int mmc_clk_io_on(int sdc_no) +{

• unsigned int rval;
• unsigned int pll5_clk;
• unsigned int divider;
• struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no];
• static struct sunxi_gpio *gpio_c =

•    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C];
  

• static struct sunxi_gpio *gpio_f =

•    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F];
  

+#if CONFIG_MMC1_PG

• static struct sunxi_gpio *gpio_g =

•    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G];
  

+#endif

• static struct sunxi_gpio *gpio_h =

•    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H];
  

• static struct sunxi_gpio *gpio_i =

•    &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I];
  

• struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;

^ Castings are ugly; rework with a temporary variable.

• debug("init mmc %d clock and io\n", sdc_no);
• /* config gpio */
• switch (sdc_no) {
• case 0:

• /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */
  

• writel(0x222222, &gpio_f->cfg[0]);
  

• writel(0x555, &gpio_f->pull[0]);
  

• writel(0xaaa, &gpio_f->drv[0]);
  

• break;
  

• case 1:

+#if CONFIG_MMC1_PG

• /* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */
  

• writel(0x444444, &gpio_g->cfg[0]);
  

• writel(0x555, &gpio_g->pull[0]);
  

• writel(0xaaa, &gpio_g->drv[0]);
  

+#else

• /* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */
  

• writel(0x55 << 24, &gpio_h->cfg[2]);
  

• writel(0x5555, &gpio_h->cfg[3]);
  

• writel(0x555 << 12, &gpio_h->pull[1]);
  

• writel(0xaaa << 12, &gpio_h->drv[1]);
  

+#endif

• break;
  

• case 2:

• /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
  

• writel(0x33 << 24, &gpio_c->cfg[0]);
  

• writel(0x3333, &gpio_c->cfg[1]);
  

• writel(0x555 << 12, &gpio_c->pull[0]);
  

• writel(0xaaa << 12, &gpio_c->drv[0]);
  

• break;
  

• case 3:

• /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */
  

• writel(0x2222 << 16, &gpio_i->cfg[0]);
  

• writel(0x22, &gpio_i->cfg[1]);
  

• writel(0x555 << 8, &gpio_i->pull[0]);
  

• writel(0x555 << 8, &gpio_i->drv[0]);
  

• break;
  

• default:

• return -1;
  

• }

Lots of magic constants. I have no idea what's going on here. Use a few defines.

• /* config ahb clock */
• rval = readl(&ccm->ahb_gate0);
• rval |= (1 << (8 + sdc_no));
• writel(rval, &ccm->ahb_gate0);
• /* config mod clock */
• pll5_clk = clock_get_pll5();
• if (pll5_clk > 400000000)

• divider = 4;
  

• else

• divider = 3;
  

• writel((0x1 << 31) | (0x2 << 24) | divider, mmchost->mclkreg);
• mmchost->mod_clk = pll5_clk / (divider + 1);
• dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100);
• dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100);
• dumphex32("mmc", (char *)mmchost->reg, 0x100);
• dumpmmcreg(mmchost->reg);
• return 0;

+}

+static int mmc_update_clk(struct mmc *mmc) +{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• unsigned int cmd;
• unsigned timeout = 0xfffff;
• cmd = (0x1 << 31) | (0x1 << 21) | (0x1 << 13);
• writel(cmd, &mmchost->reg->cmd);
• while ((readl(&mmchost->reg->cmd) & (0x1 << 31)) && timeout--);
• if (!timeout)

• return -1;
  

^ Eeek! Use udelay and a time based timeout.

• writel(readl(&mmchost->reg->rint), &mmchost->reg->rint);

^ Same here - Not even a timeout?

• return 0;

+}

+static int mmc_config_clock(struct mmc *mmc, unsigned div) +{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• unsigned rval = readl(&mmchost->reg->clkcr);
• /*

• * CLKCREG[7:0]: divider
  

• * CLKCREG[16]:  on/off
  

• * CLKCREG[17]:  power save
  

• */
  

• /* Disable Clock */
• rval &= ~(0x1 << 16);
• writel(rval, &mmchost->reg->clkcr);
• if (mmc_update_clk(mmc))

• return -1;
  

• /* Change Divider Factor */
• rval &= ~(0xff);
• rval |= div;
• writel(rval, &mmchost->reg->clkcr);
• if (mmc_update_clk(mmc))

• return -1;
  

• /* Re-enable Clock */
• rval |= (0x1 << 16);

#define ?

• writel(rval, &mmchost->reg->clkcr);
• if (mmc_update_clk(mmc))

• return -1;
  

• return 0;

+}

+static void mmc_set_ios(struct mmc *mmc) +{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• unsigned int clkdiv = 0;
• debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n",

•      mmc->bus_width, mmc->clock, mmchost->mod_clk);
  

• /* Change clock first */
• clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2;
• if (mmc->clock)

• if (mmc_config_clock(mmc, clkdiv)) {
  

• 	mmchost->fatal_err = 1;
  

• 	return;
  

• }
  

Ambiguous formatting. Use { }

• /* Change bus width */
• if (mmc->bus_width == 8)

• writel(0x2, &mmchost->reg->width);
  

• else if (mmc->bus_width == 4)

• writel(0x1, &mmchost->reg->width);
  

• else

• writel(0x0, &mmchost->reg->width);
  

+}

+static int mmc_core_init(struct mmc *mmc) +{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• /* Reset controller */
• writel(0x7, &mmchost->reg->gctrl);

Magic value again.

• return 0;

+}

+static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• unsigned i;
• unsigned byte_cnt = data->blocksize * data->blocks;
• unsigned *buff;
• unsigned timeout = 0xfffff;
• if (data->flags & MMC_DATA_READ) {

• buff = (unsigned int *)data->dest;
  

• for (i = 0; i < (byte_cnt >> 2); i++) {
  

• 	while (--timeout &&
  

• 		 (readl(&mmchost->reg->status) & (0x1 << 2)));
  

• 	if (timeout <= 0)
  

• 		goto out;
  

• 	buff[i] = readl(mmchost->database);
  

• 	timeout = 0xfffff;
  

• }
  

• } else {

• buff = (unsigned int *)data->src;
  

• for (i = 0; i < (byte_cnt >> 2); i++) {
  

• 	while (--timeout &&
  

• 		 (readl(&mmchost->reg->status) & (0x1 << 3)));
  

• 	if (timeout <= 0)
  

• 		goto out;
  

• 	writel(buff[i], mmchost->database);
  

• 	timeout = 0xfffff;
  

• }
  

• }

^ Timeouts using time values? udelay? See above.

+out:

• if (timeout <= 0)

• return -1;
  

• return 0;

+}

+static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) +{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• unsigned byte_cnt = data->blocksize * data->blocks;
• unsigned char *buff;
• unsigned des_idx = 0;
• unsigned buff_frag_num =

• (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT;
  

• unsigned remain;
• unsigned i, rval;
• ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num);
• buff = data->flags & MMC_DATA_READ ?

•    (unsigned char *)data->dest : (unsigned char *)data->src;
  

• remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1);
• if (!remain)

• remain = SDXC_DES_BUFFER_MAX_LEN;
  

• flush_cache((unsigned long)buff, (unsigned long)byte_cnt);
• for (i = 0; i < buff_frag_num; i++, des_idx++) {

• memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des));
  

• pdes[des_idx].des_chain = 1;
  

• pdes[des_idx].own = 1;
  

• pdes[des_idx].dic = 1;
  

• if (buff_frag_num > 1 && i != buff_frag_num - 1)
  

• 	pdes[des_idx].data_buf1_sz =
  

• 	    (SDXC_DES_BUFFER_MAX_LEN -
  

• 	     1) & SDXC_DES_BUFFER_MAX_LEN;
  

• else
  

• 	pdes[des_idx].data_buf1_sz = remain;
  

• pdes[des_idx].buf_addr_ptr1 =
  

•     (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN;
  

• if (i == 0)
  

• 	pdes[des_idx].first_des = 1;
  

• if (i == buff_frag_num - 1) {
  

• 	pdes[des_idx].dic = 0;
  

• 	pdes[des_idx].last_des = 1;
  

• 	pdes[des_idx].end_of_ring = 1;
  

• 	pdes[des_idx].buf_addr_ptr2 = 0;
  

• } else {
  

• 	pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1];
  

• }
  

• debug("frag %d, remain %d, des[%d](%08x): ",
  

•       i, remain, des_idx, (u32)&pdes[des_idx]);
  

• debug("[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n",
  

•       (u32)((u32 *)&pdes[des_idx])[0],
  

•       (u32)((u32 *)&pdes[des_idx])[1],
  

•       (u32)((u32 *)&pdes[des_idx])[2],
  

•       (u32)((u32 *)&pdes[des_idx])[3]);
  

• }
• flush_cache((unsigned long)pdes,

•     sizeof(struct sunxi_mmc_des) * (des_idx + 1));
  

• /*

• * GCTRLREG
  

• * GCTRL[2]     : DMA reset
  

• * GCTRL[5]     : DMA enable
  

• *
  

• * IDMACREG
  

• * IDMAC[0]     : IDMA soft reset
  

• * IDMAC[1]     : IDMA fix burst flag
  

• * IDMAC[7]     : IDMA on
  

• *
  

• * IDIECREG
  

• * IDIE[0]      : IDMA transmit interrupt flag
  

• * IDIE[1]      : IDMA receive interrupt flag
  

• */
  

• rval = readl(&mmchost->reg->gctrl);
• /* Enable DMA */
• writel(rval | (0x1 << 5) | (0x1 << 2), &mmchost->reg->gctrl);
• /* Reset iDMA */
• writel((0x1 << 0), &mmchost->reg->dmac);
• /* Enable iDMA */
• writel((0x1 << 1) | (1 << 7), &mmchost->reg->dmac);
• rval = readl(&mmchost->reg->idie) & (~3);
• if (data->flags & MMC_DATA_WRITE)

• rval |= (0x1 << 0);
  

• else

• rval |= (0x1 << 1);
  

• writel(rval, &mmchost->reg->idie);
• writel((u32) pdes, &mmchost->reg->dlba);
• writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3),

•       &mmchost->reg->ftrglevel);
  

^ #define again?

• return 0;

+}

+static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,

• 	struct mmc_data *data)
  

+{

• struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv;
• unsigned int cmdval = 0x80000000;
• signed int timeout = 0;
• int error = 0;
• unsigned int status = 0;
• unsigned int usedma = 0;
• unsigned int bytecnt = 0;
• if (mmchost->fatal_err)

• return -1;
  

• if (cmd->resp_type & MMC_RSP_BUSY)

• debug("mmc cmd %d check rsp busy\n", cmd->cmdidx);
  

• if (cmd->cmdidx == 12)

• return 0;
  

• /*

• * CMDREG
  

• * CMD[5:0]     : Command index
  

• * CMD[6]       : Has response
  

• * CMD[7]       : Long response
  

• * CMD[8]       : Check response CRC
  

• * CMD[9]       : Has data
  

• * CMD[10]      : Write
  

• * CMD[11]      : Steam mode
  

• * CMD[12]      : Auto stop
  

• * CMD[13]      : Wait previous over
  

• * CMD[14]      : About cmd
  

• * CMD[15]      : Send initialization
  

• * CMD[21]      : Update clock
  

• * CMD[31]      : Load cmd
  

• */
  

• if (!cmd->cmdidx)

• cmdval |= (0x1 << 15);
  

• if (cmd->resp_type & MMC_RSP_PRESENT)

• cmdval |= (0x1 << 6);
  

• if (cmd->resp_type & MMC_RSP_136)

• cmdval |= (0x1 << 7);
  

• if (cmd->resp_type & MMC_RSP_CRC)

• cmdval |= (0x1 << 8);
  

• if (data) {

• if ((u32) data->dest & 0x3) {
  

• 	error = -1;
  

• 	goto out;
  

• }
  

• cmdval |= (0x1 << 9) | (0x1 << 13);
  

• if (data->flags & MMC_DATA_WRITE)
  

• 	cmdval |= (0x1 << 10);
  

• if (data->blocks > 1)
  

• 	cmdval |= (0x1 << 12);
  

• writel(data->blocksize, &mmchost->reg->blksz);
  

• writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt);
  

• }
• debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no,

•      cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg);
  

• writel(cmd->cmdarg, &mmchost->reg->arg);
• if (!data)

• writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
  

• /*

• * transfer data and check status
  

• * STATREG[2] : FIFO empty
  

• * STATREG[3] : FIFO full
  

• */
  

• if (data) {

• int ret = 0;
  

• bytecnt = data->blocksize * data->blocks;
  

• debug("trans data %d bytes\n", bytecnt);
  

+#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD)

• if (bytecnt > 64) {
  

+#else

• if (0) {
  

+#endif

• 	usedma = 1;
  

• 	writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 31),
  

• 	       &mmchost->reg->gctrl);
  

• 	ret = mmc_trans_data_by_dma(mmc, data);
  

• 	writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
  

• } else {
  

• 	writel(readl(&mmchost->reg->gctrl) | 0x1 << 31,
  

• 	       &mmchost->reg->gctrl);
  

• 	writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd);
  

• 	ret = mmc_trans_data_by_cpu(mmc, data);
  

• }
  

• if (ret) {
  

• 	error = readl(&mmchost->reg->rint) & 0xbfc2;
  

• 	error = TIMEOUT;
  

• 	goto out;
  

• }
  

• }
• timeout = 0xfffff;
• do {

• status = readl(&mmchost->reg->rint);
  

• if (!timeout-- || (status & 0xbfc2)) {
  

• 	error = status & 0xbfc2;
  

• 	debug("cmd timeout %x\n", error);
  

• 	error = TIMEOUT;
  

• 	goto out;
  

• }
  

^ Again timeouts without using time values.

• } while (!(status & 0x4));
• if (data) {

• unsigned done = 0;
  

• timeout = usedma ? 0xffff * bytecnt : 0xffff;
  

• debug("cacl timeout %x\n", timeout);
  

• do {
  

• 	status = readl(&mmchost->reg->rint);
  

• 	if (!timeout-- || (status & 0xbfc2)) {
  

• 		error = status & 0xbfc2;
  

• 		debug("data timeout %x\n", error);
  

• 		error = TIMEOUT;
  

• 		goto out;
  

• 	}
  

• 	if (data->blocks > 1)
  

• 		done = status & (0x1 << 14);
  

• 	else
  

• 		done = status & (0x1 << 3);
  

^ Timeouts?

• } while (!done);
  

• }
• if (cmd->resp_type & MMC_RSP_BUSY) {

• timeout = 0xfffff;
  

• do {
  

• 	status = readl(&mmchost->reg->status);
  

• 	if (!timeout--) {
  

• 		debug("busy timeout\n");
  

• 		error = TIMEOUT;
  

• 		goto out;
  

• 	}
  

• } while (status & (1 << 9));
  

^ You get the idea... Timeouts. And #defines

• }
• if (cmd->resp_type & MMC_RSP_136) {

• cmd->response[0] = readl(&mmchost->reg->resp3);
  

• cmd->response[1] = readl(&mmchost->reg->resp2);
  

• cmd->response[2] = readl(&mmchost->reg->resp1);
  

• cmd->response[3] = readl(&mmchost->reg->resp0);
  

• debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
  

•       cmd->response[3], cmd->response[2],
  

•       cmd->response[1], cmd->response[0]);
  

• } else {

• cmd->response[0] = readl(&mmchost->reg->resp0);
  

• debug("mmc resp 0x%08x\n", cmd->response[0]);
  

• }

+out:

• if (data && usedma) {

• /* IDMASTAREG
  

•  * IDST[0] : idma tx int
  

•  * IDST[1] : idma rx int
  

•  * IDST[2] : idma fatal bus error
  

•  * IDST[4] : idma descriptor invalid
  

•  * IDST[5] : idma error summary
  

•  * IDST[8] : idma normal interrupt sumary
  

•  * IDST[9] : idma abnormal interrupt sumary
  

•  */
  

• status = readl(&mmchost->reg->idst);
  

• writel(status, &mmchost->reg->idst);
  

• writel(0, &mmchost->reg->idie);
  

• writel(0, &mmchost->reg->dmac);
  

• writel(readl(&mmchost->reg->gctrl) & ~(0x1 << 5),
  

•        &mmchost->reg->gctrl);
  

• }
• if (error < 0) {

• writel(0x7, &mmchost->reg->gctrl);
  

• mmc_update_clk(mmc);
  

• }
• writel(0xffffffff, &mmchost->reg->rint);
• writel(readl(&mmchost->reg->gctrl) | (1 << 1), &mmchost->reg->gctrl);
• return error;

+}

+int sunxi_mmc_init(int sdc_no) +{

• struct mmc *mmc;
• memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc));
• memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host));
• mmc = &mmc_dev[sdc_no];
• sprintf(mmc->name, "SUNXI SD/MMC");
• mmc->priv = &mmc_host[sdc_no];
• mmc->send_cmd = mmc_send_cmd;
• mmc->set_ios = mmc_set_ios;
• mmc->init = mmc_core_init;
• mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
• mmc->host_caps = MMC_MODE_4BIT;
• mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
• mmc->f_min = 400000;
• mmc->f_max = 52000000;
• mmc_resource_init(sdc_no);
• mmc_clk_io_on(sdc_no);
• mmc_register(mmc);

^ The mmc_registeration sequence has changed, but not landed at master yet.

• return 0;

+} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index bdfc169..1afdeb2 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -74,6 +74,16 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING

+/* mmc config */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SUNXI +#define CONFIG_MMC_SUNXI_SLOT 0 +#define CONFIG_MMC_SUNXI_USE_DMA +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */

/*

• Size of malloc() pool
• 1MB = 0x100000, 0x100000 = 1024 * 1024

@@ -118,6 +128,7 @@ #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ #define CONFIG_IDENT_STRING " Allwinner Technology"

+#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */

#define CONFIG_BOOTDELAY 3

1.8.5.3

---

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-- Pantelis