Hi Daniel, I like the way you implemented the cache code to try to make it generic across different MIPS generations. Unfortunately, its a complete replacement of the function implementation for our needs because of our unique cache design. Its not you, its us. :) I’ll submit a patch to make it weak. BR, Alex
On Dec 23, 2019, at 10:33 AM, Daniel Schwierzeck daniel.schwierzeck@gmail.com wrote:
Hi Alex,
Am 21.12.19 um 01:56 schrieb Alex Nemirovsky:
Hello Daniel et. all,
We have a need to override what is done inside arch/mips/lib/cache.c::flush_dcache_range() for our SoC/board.
Easiest approach seems to be making the function __weak upstream. i.e.
-void flush_dcache_range(ulong start_addr, ulong stop) +void __weak flush_dcache_range(ulong start_addr, ulong stop)
thoughts?
could you explain what is different? Is it some propietary vendor/SoC specific functionality or only special for a MIPS core family?
If possible I'd like to keep the cache code in one place and maybe extend it with some feature toggled code. Alternatively flush_dcache_range() could call a weak function as an extension point (similar to __ioremap_mode()). Only if you really needed to completely replace the code, you could submit a patch to make flush_dcache_range() weak.
--
- Daniel