On Fri, Oct 7, 2016 at 9:44 PM, linux-kernel-dev@beckhoff.com wrote:
From: Patrick Bruenn p.bruenn@beckhoff.com
Add CX9020 board based on mx53loco. Add simplified imx53 base device tree from kernel v4.8-rc8, to reuse serial_mxc with DTE and prepare for device tree migration of other functions and imx53 devices.
The CX9020 differs from i.MX53 Quick Start Board by:
- use uart2 instead of uart1
- DVI-D connector instead of VGA
- no audio
- CCAT FPGA connected to emi
- enable rtc
Signed-off-by: Patrick Bruenn p.bruenn@beckhoff.com
Changes in v2:
- remove #include <asm/errno.h> from mx53cx9020.c
- remove obsolete CONFIG_CMD_CCAT from mx53cx9020.h
arch/arm/Kconfig | 7 + arch/arm/dts/Makefile | 2 + arch/arm/dts/imx53-cx9020.dts | 26 ++ arch/arm/dts/imx53.dtsi | 41 ++ board/beckhoff/mx53cx9020/Kconfig | 15 + board/beckhoff/mx53cx9020/MAINTAINERS | 6 + board/beckhoff/mx53cx9020/Makefile | 9 + board/beckhoff/mx53cx9020/imximage.cfg | 82 ++++ board/beckhoff/mx53cx9020/mx53cx9020.c | 563 +++++++++++++++++++++++++++ board/beckhoff/mx53cx9020/mx53cx9020_video.c | 83 ++++ configs/mx53cx9020_defconfig | 19 + include/configs/mx53cx9020.h | 208 ++++++++++ 12 files changed, 1061 insertions(+) create mode 100644 arch/arm/dts/imx53-cx9020.dts create mode 100644 arch/arm/dts/imx53.dtsi create mode 100644 board/beckhoff/mx53cx9020/Kconfig create mode 100644 board/beckhoff/mx53cx9020/MAINTAINERS create mode 100644 board/beckhoff/mx53cx9020/Makefile create mode 100644 board/beckhoff/mx53cx9020/imximage.cfg create mode 100644 board/beckhoff/mx53cx9020/mx53cx9020.c create mode 100644 board/beckhoff/mx53cx9020/mx53cx9020_video.c create mode 100644 configs/mx53cx9020_defconfig create mode 100644 include/configs/mx53cx9020.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f55d5b2..ece610a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -480,6 +480,12 @@ config TARGET_MX53LOCO bool "Support mx53loco" select CPU_V7
+config TARGET_MX53CX9020
bool "Support mx53cx9020"select CPU_V7select DMselect DM_SERIALconfig TARGET_MX53SMD bool "Support mx53smd" select CPU_V7 @@ -965,6 +971,7 @@ source "board/freescale/mx51evk/Kconfig" source "board/freescale/mx53ard/Kconfig" source "board/freescale/mx53evk/Kconfig" source "board/freescale/mx53loco/Kconfig" +source "board/beckhoff/mx53cx9020/Kconfig" source "board/freescale/mx53smd/Kconfig" source "board/freescale/s32v234evb/Kconfig" source "board/freescale/vf610twr/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 04d47e7..3f753ba 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -286,6 +286,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \ imx6dl-icore.dtb \ imx6q-icore.dtb
+dtb-$(CONFIG_TARGET_MX53CX9020) += imx53-cx9020.dtb
This should be MX arch config entry, not the target one.
dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2l-evm.dtb \ k2e-evm.dtb \ diff --git a/arch/arm/dts/imx53-cx9020.dts b/arch/arm/dts/imx53-cx9020.dts new file mode 100644 index 0000000..4fc6214 --- /dev/null +++ b/arch/arm/dts/imx53-cx9020.dts @@ -0,0 +1,26 @@ +/*
- Copyright 2016 Beckhoff Automation
- Copyright 2011 Freescale Semiconductor, Inc.
- Copyright 2011 Linaro Ltd.
- SPDX-License-Identifier: GPL-2.0+ or X11
- */
+/dts-v1/; +#include "imx53.dtsi"
+/ {
model = "Beckhoff CX9020-0100 i.MX53";compatible = "fsl,imx53-qsb", "fsl,imx53";chosen {stdout-path = &uart2;};+};
+&uart2 {
pinctrl-names = "default";uart-has-rtscts;fsl,dte-mode;status = "okay";+}; diff --git a/arch/arm/dts/imx53.dtsi b/arch/arm/dts/imx53.dtsi new file mode 100644 index 0000000..3da0765 --- /dev/null +++ b/arch/arm/dts/imx53.dtsi @@ -0,0 +1,41 @@ +/*
- Copyright 2016 Beckhoff Automation
- Copyright 2011 Freescale Semiconductor, Inc.
- Copyright 2011 Linaro Ltd.
- The code contained herein is licensed under the GNU General Public
- License. You may obtain a copy of the GNU General Public License
- Version 2 or later at the following locations:
- */
+#include "skeleton.dtsi"
+/ {
aliases {serial1 = &uart2;};soc {#address-cells = <1>;#size-cells = <1>;compatible = "simple-bus";ranges;aips@50000000 { /* AIPS1 */compatible = "fsl,aips-bus", "simple-bus";#address-cells = <1>;#size-cells = <1>;reg = <0x50000000 0x10000000>;ranges;uart2: serial@53fc0000 {compatible = "fsl,imx7d-uart", "fsl,imx53-uart", "fsl,imx21-uart";reg = <0x53fc0000 0x4000>;status = "disabled";};};};+}; diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig new file mode 100644 index 0000000..6b60ce3 --- /dev/null +++ b/board/beckhoff/mx53cx9020/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MX53CX9020
+config SYS_BOARD
default "mx53cx9020"+config SYS_VENDOR
default "beckhoff"+config SYS_SOC
default "mx5"+config SYS_CONFIG_NAME
default "mx53cx9020"+endif diff --git a/board/beckhoff/mx53cx9020/MAINTAINERS b/board/beckhoff/mx53cx9020/MAINTAINERS new file mode 100644 index 0000000..f84413e --- /dev/null +++ b/board/beckhoff/mx53cx9020/MAINTAINERS @@ -0,0 +1,6 @@ +MX53 CX9020 +M: Patrick Bruenn p.bruenn@beckhoff.com +S: Maintained +F: board/beckhoff/mx53cx9020/ +F: include/configs/mx53cx9020.h +F: configs/mx53cx9020_defconfig diff --git a/board/beckhoff/mx53cx9020/Makefile b/board/beckhoff/mx53cx9020/Makefile new file mode 100644 index 0000000..a01c0f1 --- /dev/null +++ b/board/beckhoff/mx53cx9020/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG +# Patrick Bruenn p.bruenn@beckhoff.com +# +# SPDX-License-Identifier: GPL-2.0+ +#
+obj-y += mx53cx9020.o +obj-$(CONFIG_VIDEO) += mx53cx9020_video.o diff --git a/board/beckhoff/mx53cx9020/imximage.cfg b/board/beckhoff/mx53cx9020/imximage.cfg new file mode 100644 index 0000000..c6bdc72 --- /dev/null +++ b/board/beckhoff/mx53cx9020/imximage.cfg @@ -0,0 +1,82 @@ +/*
- Copyright (C) 2015 Beckhoff Automation GmbH
- Patrick Bruenn p.bruenn@beckhoff.com
- Based on Freescale's Linux i.MX mx53loco/imximage.cfg file:
- Copyright (C) 2011 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+/* image version */ +IMAGE_VERSION 2
+/*
- Boot Device : one of
- spi, sd (the board has no nand neither onenand)
- */
+BOOT_FROM sd
+/*
- Device Configuration Data (DCD)
- Each entry must have the format:
- Addr-type Address Value
- where:
Addr-type register length (1,2 or 4 bytes)
Address absolute address of the register
value value to be stored in the register- */
+DATA 4 0x53fa8554 0x00300000 +DATA 4 0x53fa8558 0x00300040 +DATA 4 0x53fa8560 0x00300000 +DATA 4 0x53fa8564 0x00300040 +DATA 4 0x53fa8568 0x00300040 +DATA 4 0x53fa8570 0x00300000 +DATA 4 0x53fa8574 0x00300000 +DATA 4 0x53fa8578 0x00300000 +DATA 4 0x53fa857c 0x00300040 +DATA 4 0x53fa8580 0x00300040 +DATA 4 0x53fa8584 0x00300000 +DATA 4 0x53fa8588 0x00300000 +DATA 4 0x53fa8590 0x00300040 +DATA 4 0x53fa8594 0x00300000 +DATA 4 0x53fa86f0 0x00300000 +DATA 4 0x53fa86f4 0x00000000 +DATA 4 0x53fa86fc 0x00000000 +DATA 4 0x53fa8714 0x00000000 +DATA 4 0x53fa8718 0x00300000 +DATA 4 0x53fa871c 0x00300000 +DATA 4 0x53fa8720 0x00300000 +DATA 4 0x53fa8724 0x00000000 +DATA 4 0x53fa8728 0x00300000 +DATA 4 0x53fa872c 0x00300000 +DATA 4 0x63fd9088 0x35343535 +DATA 4 0x63fd9090 0x4d444c44 +DATA 4 0x63fd907c 0x01370138 +DATA 4 0x63fd9080 0x013b013c +DATA 4 0x63fd9018 0x00011740 +DATA 4 0x63fd9000 0x83190000 +DATA 4 0x63fd900c 0x40425333 +DATA 4 0x63fd9010 0xb68e8a63 +DATA 4 0x63fd9014 0x01ff00db +DATA 4 0x63fd902c 0x000026d2 +DATA 4 0x63fd9030 0x009f0e21 +DATA 4 0x63fd9008 0x12273030 +DATA 4 0x63fd9004 0x0002002d +DATA 4 0x63fd901c 0x00008032 +DATA 4 0x63fd901c 0x00008033 +DATA 4 0x63fd901c 0x00028031 +DATA 4 0x63fd901c 0x052080b0 +DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd901c 0x0000803a +DATA 4 0x63fd901c 0x0000803b +DATA 4 0x63fd901c 0x00028039 +DATA 4 0x63fd901c 0x05208138 +DATA 4 0x63fd901c 0x04008048 +DATA 4 0x63fd9020 0x00005800 +DATA 4 0x63fd9040 0x05380003 +DATA 4 0x63fd9058 0x00022227 +DATA 4 0x63fd901c 0x00000000 diff --git a/board/beckhoff/mx53cx9020/mx53cx9020.c b/board/beckhoff/mx53cx9020/mx53cx9020.c new file mode 100644 index 0000000..c92ec15 --- /dev/null +++ b/board/beckhoff/mx53cx9020/mx53cx9020.c @@ -0,0 +1,563 @@ +/*
- Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
- Patrick Bruenn p.bruenn@beckhoff.com
- Based on Freescale's Linux i.MX mx53loco.c file:
- Copyright (C) 2011 Freescale Semiconductor, Inc.
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux-mx53.h> +#include <asm/arch/clock.h> +#include <asm/imx-common/mx5_video.h> +#include <netdev.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/gpio.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> +#include <fs.h> +#include <dm/platdata.h> +#include <dm/platform_data/serial_mxc.h>
+enum LED_GPIOS {
GPIO_SD1_CD = IMX_GPIO_NR(1, 1),GPIO_SD2_CD = IMX_GPIO_NR(1, 4),GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),GPIO_C3_DONE = IMX_GPIO_NR(6, 9),+};
+#define CCAT_BASE_ADDR ((void *)0xf0000000) +#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32)) +#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12) +static const char CCAT_SIGNATURE[] = "CCAT";
+static const u32 CCAT_MODE_CONFIG = 0x0024DC81; +static const u32 CCAT_MODE_RUN = 0x0033DC8F;
+DECLARE_GLOBAL_DATA_PTR;
+static uint32_t mx53_dram_size[2];
+phys_size_t get_effective_memsize(void) +{
/** WARNING: We must override get_effective_memsize() function here* to report only the size of the first DRAM bank. This is to make* U-Boot relocator place U-Boot into valid memory, that is, at the* end of the first DRAM bank. If we did not override this function* like so, U-Boot would be placed at the address of the first DRAM* bank + total DRAM size - sizeof(uboot), which in the setup where* each DRAM bank contains 512MiB of DRAM would result in placing* U-Boot into invalid memory area close to the end of the first* DRAM bank.*/return mx53_dram_size[0];+}
+int dram_init(void) +{
mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];return 0;+}
+void dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;gd->bd->bi_dram[0].size = mx53_dram_size[0];gd->bd->bi_dram[1].start = PHYS_SDRAM_2;gd->bd->bi_dram[1].size = mx53_dram_size[1];+}
+u32 get_board_rev(void) +{
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;struct fuse_bank *bank = &iim->bank[0];struct fuse_bank0_regs *fuse =(struct fuse_bank0_regs *)bank->fuse_regs;int rev = readl(&fuse->gp[6]);return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;+}
+/*
- Set CCAT mode
- @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
- */
+void weim_cs0_settings(u32 mode) +{
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;writel(0x0, &weim_regs->cs0gcr1);writel(mode, &weim_regs->cs0gcr1);writel(0x00001002, &weim_regs->cs0gcr2);writel(0x04000000, &weim_regs->cs0rcr1);writel(0x00000000, &weim_regs->cs0rcr2);writel(0x04000000, &weim_regs->cs0wcr1);writel(0x00000000, &weim_regs->cs0wcr2);+}
+static void setup_iomux_eim(void) +{
static const iomux_v3_cfg_t eim_pads[] = {NEW_PAD_CTRL(MX53_PAD_EIM_OE__EMI_WEIM_OE,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_WAIT__EMI_WEIM_WAIT,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_LBA__EMI_WEIM_LBA,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_RW__EMI_WEIM_RW,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_EB0__EMI_WEIM_EB_0,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_EB1__EMI_WEIM_EB_1,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_EB2__EMI_WEIM_EB_2,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_EB3__EMI_WEIM_EB_3,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_CS0__EMI_WEIM_CS_0,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A16__EMI_WEIM_A_16,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A17__EMI_WEIM_A_17,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A18__EMI_WEIM_A_18,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A19__EMI_WEIM_A_19,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A20__EMI_WEIM_A_20,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A21__EMI_WEIM_A_21,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_A22__EMI_WEIM_A_22,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA8__EMI_NAND_WEIM_DA_8,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA9__EMI_NAND_WEIM_DA_9,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA10__EMI_NAND_WEIM_DA_10,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA11__EMI_NAND_WEIM_DA_11,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA12__EMI_NAND_WEIM_DA_12,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA13__EMI_NAND_WEIM_DA_13,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA14__EMI_NAND_WEIM_DA_14,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_EIM_DA15__EMI_NAND_WEIM_DA_15,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__EMI_NANDF_D_8,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__EMI_NANDF_D_9,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__EMI_NANDF_D_10,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__EMI_NANDF_D_11,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__EMI_NANDF_D_12,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__EMI_NANDF_D_13,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__EMI_NANDF_D_14,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__EMI_NANDF_D_15,PAD_CTL_PKE | PAD_CTL_DSE_HIGH),};imx_iomux_v3_setup_multiple_pads(eim_pads, ARRAY_SIZE(eim_pads));imx_iomux_v3_setup_pad(MX53_PAD_NANDF_CLE__GPIO6_7);gpio_direction_input(GPIO_C3_STATUS);imx_iomux_v3_setup_pad(MX53_PAD_NANDF_WP_B__GPIO6_9);gpio_direction_input(GPIO_C3_DONE);imx_iomux_v3_setup_pad(MX53_PAD_NANDF_ALE__GPIO6_8);gpio_direction_output(GPIO_C3_CONFIG, 1);weim_cs0_settings(CCAT_MODE_RUN);+}
+static void setup_iomux_sups(void) +{
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_EIM_D31__GPIO3_31,PAD_CTL_PUS_100K_DOWN));gpio_direction_input(GPIO_SUPS_INT);static const int BLINK_INTERVALL = 50000;int status = 1;while (gpio_get_value(GPIO_SUPS_INT)) {/* signal "CX SUPS power fail" */gpio_set_value(GPIO_LED_PWR_R,(++status / BLINK_INTERVALL) % 2);}/* signal "CX power up" */gpio_set_value(GPIO_LED_PWR_R, 1);+}
+static void setup_iomux_leds(void) +{
imx_iomux_v3_setup_pad(MX53_PAD_EIM_D16__GPIO3_16);gpio_direction_output(GPIO_LED_SD2_R, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D17__GPIO3_17);gpio_direction_output(GPIO_LED_SD2_B, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D18__GPIO3_18);gpio_direction_output(GPIO_LED_SD2_G, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D19__GPIO3_19);gpio_direction_output(GPIO_LED_SD1_R, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D20__GPIO3_20);gpio_direction_output(GPIO_LED_SD1_B, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D21__GPIO3_21);gpio_direction_output(GPIO_LED_SD1_G, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D22__GPIO3_22);gpio_direction_output(GPIO_LED_PWR_R, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D23__GPIO3_23);gpio_direction_output(GPIO_LED_PWR_B, 0);imx_iomux_v3_setup_pad(MX53_PAD_EIM_D24__GPIO3_24);gpio_direction_output(GPIO_LED_PWR_G, 0);+}
+#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)+#define MX53_PAD_EIM_D26__UART2_RXD_MUX \
IOMUX_PAD(0x48c, 0x144, 2, 0x880, 0, MX53_UART_PAD_CTRL)+#define MX53_PAD_EIM_D27__UART2_TXD_MUX \
IOMUX_PAD(0x490, 0x148, 2, 0x000, 0, MX53_UART_PAD_CTRL)+#define MX53_PAD_EIM_D28__UART2_RTS \
IOMUX_PAD(0x494, 0x14c, 2, 0x87C, 0, MX53_UART_PAD_CTRL)+#define MX53_PAD_EIM_D29__UART2_CTS \
IOMUX_PAD(0x498, 0x150, 2, 0x000, 0, MX53_UART_PAD_CTRL)+static void setup_iomux_uart(void) +{
static const iomux_v3_cfg_t uart_pads[] = {NEW_PAD_CTRL(MX53_PAD_EIM_D26__UART2_RXD_MUX, UART_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_EIM_D27__UART2_TXD_MUX, UART_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_EIM_D28__UART2_RTS, UART_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_EIM_D29__UART2_CTS, UART_PAD_CTRL),};imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));+}
+#ifdef CONFIG_USB_EHCI_MX5 +int board_ehci_hcd_init(int port) +{
/* request VBUS power enable pin, GPIO7_8 */imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);gpio_direction_output(IMX_GPIO_NR(7, 8), 1);return 0;+} +#endif
+static void setup_iomux_fec(void) +{
static const iomux_v3_cfg_t fec_pads[] = {NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP |PAD_CTL_ODE),NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,PAD_CTL_HYS | PAD_CTL_PKE),NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,PAD_CTL_HYS | PAD_CTL_PKE),NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,PAD_CTL_HYS | PAD_CTL_PKE),NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,PAD_CTL_HYS | PAD_CTL_PKE),NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,PAD_CTL_HYS | PAD_CTL_PKE),};imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));+}
+#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = {
{MMC_SDHC1_BASE_ADDR},{MMC_SDHC2_BASE_ADDR},+};
+int board_mmc_getcd(struct mmc *mmc) +{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;int ret;imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);gpio_direction_input(GPIO_SD1_CD);imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);gpio_direction_input(GPIO_SD2_CD);if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)ret = !gpio_get_value(GPIO_SD1_CD);elseret = !gpio_get_value(GPIO_SD2_CD);return ret;+}
+#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)+#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)+int board_mmc_init(bd_t *bis) +{
static const iomux_v3_cfg_t sd1_pads[] = {NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),MX53_PAD_GPIO_1__GPIO1_1,};static const iomux_v3_cfg_t sd2_pads[] = {NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),MX53_PAD_GPIO_4__GPIO1_4,};
Since, it's have dts support please use pinctrl driver for pads and mux atleast for supporting ones.
thanks!