Andes CPU supports cache and TLB ECC. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang ycliang@andestech.com --- arch/riscv/cpu/andesv5/cpu.c | 3 ++- arch/riscv/include/asm/arch-andes/csr.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index a23b7948d9..d25ecba0e8 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -35,7 +35,8 @@ void harts_early_init(void)
mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ - MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN); + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN | \ + MCACHE_CTL_IC_ECCEN | MCACHE_CTL_DC_ECCEN | MCACHE_CTL_TLB_ECCEN);
if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl_val |= MCACHE_CTL_IC_EN; diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 3f3f05b348..028fd01c2f 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -18,11 +18,14 @@
#define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) +#define MCACHE_CTL_IC_ECCEN BIT(3) +#define MCACHE_CTL_DC_ECCEN BIT(5) #define MCACHE_CTL_CCTL_SUEN BIT(8) #define MCACHE_CTL_IC_PREFETCH_EN BIT(9) #define MCACHE_CTL_DC_PREFETCH_EN BIT(10) #define MCACHE_CTL_DC_WAROUND_EN BIT(13) #define MCACHE_CTL_L2C_WAROUND_EN BIT(15) +#define MCACHE_CTL_TLB_ECCEN BIT(18) #define MCACHE_CTL_DC_COHEN BIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20)