On Thu, Jan 07, 2021 at 11:12:16AM +0100, Marek Vasut wrote:
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words after the descriptor. Use this to pad the descriptors to cacheline size and remove the need for noncached memory altogether. Moreover, this lets Tegra use the generic cache flush / invalidate operations.
Signed-off-by: Marek Vasut marex@denx.de Cc: Joe Hershberger joe.hershberger@ni.com Cc: Patrice Chotard patrice.chotard@st.com Cc: Patrick Delaunay patrick.delaunay@st.com Cc: Ramon Fried rfried.dev@gmail.com Cc: Stephen Warren swarren@nvidia.com Tested-by: Stephen Warren swarren@nvidia.com Reviewed-by: Stephen Warren swarren@nvidia.com Tested-by: Patrice Chotard patrice.chotard@foss.st.com
Applied to u-boot/master, thanks!