This board is behind on several mandatory DM migrations and is missing OF_CONTROL support that makes other conversions impossible. Remove it.
Cc: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com Cc: Tetsuyuki Kobayashi koba@kmckk.co.jp Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-rmobile/Kconfig.32 | 4 - board/kmc/kzm9g/Kconfig | 12 - board/kmc/kzm9g/MAINTAINERS | 7 - board/kmc/kzm9g/Makefile | 6 - board/kmc/kzm9g/kzm9g.c | 373 ------------------------------- configs/kzm9g_defconfig | 47 ---- include/configs/kzm9g.h | 57 ----- 7 files changed, 506 deletions(-) delete mode 100644 board/kmc/kzm9g/Kconfig delete mode 100644 board/kmc/kzm9g/MAINTAINERS delete mode 100644 board/kmc/kzm9g/Makefile delete mode 100644 board/kmc/kzm9g/kzm9g.c delete mode 100644 configs/kzm9g_defconfig delete mode 100644 include/configs/kzm9g.h
diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-rmobile/Kconfig.32 index 27db7940e370..a07eff71dfe7 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-rmobile/Kconfig.32 @@ -83,9 +83,6 @@ config TARGET_LAGER select SPL_USE_TINY_PRINTF imply CMD_DM
-config TARGET_KZM9G - bool "KZM9D board" - config TARGET_ALT bool "Alt board" select DM @@ -157,7 +154,6 @@ source "board/renesas/blanche/Kconfig" source "board/renesas/gose/Kconfig" source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" -source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" source "board/renesas/silk/Kconfig" source "board/renesas/porter/Kconfig" diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig deleted file mode 100644 index f163efd9892b..000000000000 --- a/board/kmc/kzm9g/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_KZM9G - -config SYS_BOARD - default "kzm9g" - -config SYS_VENDOR - default "kmc" - -config SYS_CONFIG_NAME - default "kzm9g" - -endif diff --git a/board/kmc/kzm9g/MAINTAINERS b/board/kmc/kzm9g/MAINTAINERS deleted file mode 100644 index 411efd1e31e0..000000000000 --- a/board/kmc/kzm9g/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -KZM9G BOARD -M: Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com -M: Tetsuyuki Kobayashi koba@kmckk.co.jp -S: Maintained -F: board/kmc/kzm9g/ -F: include/configs/kzm9g.h -F: configs/kzm9g_defconfig diff --git a/board/kmc/kzm9g/Makefile b/board/kmc/kzm9g/Makefile deleted file mode 100644 index aebe9f3546ef..000000000000 --- a/board/kmc/kzm9g/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com -# (C) Copyright 2012 Renesas Solutions Corp. - -obj-y := kzm9g.o diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c deleted file mode 100644 index dccf4691afa8..000000000000 --- a/board/kmc/kzm9g/kzm9g.c +++ /dev/null @@ -1,373 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <common.h> -#include <cpu_func.h> -#include <init.h> -#include <net.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <netdev.h> -#include <i2c.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CS0BCR_D (0x06C00400) -#define CS4BCR_D (0x16c90400) -#define CS0WCR_D (0x55062C42) -#define CS4WCR_D (0x1e071dc3) - -#define CMNCR_BROMMD0 (1 << 21) -#define CMNCR_BROMMD1 (1 << 22) -#define CMNCR_BROMMD (CMNCR_BROMMD0|CMNCR_BROMMD1) -#define VCLKCR1_D (0x27) - -#define SMSTPCR1_CMT0 (1 << 24) -#define SMSTPCR1_I2C0 (1 << 16) -#define SMSTPCR3_USB (1 << 22) -#define SMSTPCR3_I2C1 (1 << 23) - -#define PORT32CR (0xE6051020) -#define PORT33CR (0xE6051021) -#define PORT34CR (0xE6051022) -#define PORT35CR (0xE6051023) - -static int cmp_loop(u32 *addr, u32 data, u32 cmp) -{ - int err = -1; - int timeout = 100; - u32 value; - - while (timeout > 0) { - value = readl(addr); - if ((value & data) == cmp) { - err = 0; - break; - } - timeout--; - } - - return err; -} - -/* SBSC Init function */ -static void sbsc_init(struct sh73a0_sbsc *sbsc) -{ - writel(readl(&sbsc->dllcnt0)|0x2, &sbsc->dllcnt0); - writel(0x5, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0xacc90159, &sbsc->sdcr0); - writel(0x00010059, &sbsc->sdcr1); - writel(0x50874114, &sbsc->sdwcrc0); - writel(0x33199b37, &sbsc->sdwcrc1); - writel(0x008f2313, &sbsc->sdwcrc2); - writel(0x31020707, &sbsc->sdwcr00); - writel(0x0017040a, &sbsc->sdwcr01); - writel(0x31020707, &sbsc->sdwcr10); - writel(0x0017040a, &sbsc->sdwcr11); - writel(0x055557ff, &sbsc->sddrvcr0); /* Enlarge drivability of LPDQS0-3, LPCLK */ - writel(0x30000000, &sbsc->sdwcr2); - - writel(readl(&sbsc->sdpcr) | 0x80, &sbsc->sdpcr); - cmp_loop(&sbsc->sdpcr, 0x80, 0x80); - - writel(0x00002710, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000003f, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x000001f4, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - writel(0x0000ff0a, &sbsc->sdmracr0); - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) - writel(0x0, SDMRA3A); - else - writel(0x0, SDMRA3B); - - writel(0x00000032, &sbsc->sdgencnt); - cmp_loop(&sbsc->sdgencnt, 0xffffffff, 0x0); - - if (sbsc == (struct sh73a0_sbsc *)SBSC1_BASE) { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1A); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1A); - writel(0x0, SDMRA2A); - } else { - writel(0x00002201, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000402, &sbsc->sdmracr0); - writel(0x0, SDMRA1B); - writel(0x00000203, &sbsc->sdmracr0); /* MR3 register DS=2 */ - writel(0x0, SDMRA1B); - writel(0x0, SDMRA2B); - } - - writel(0x88800004, &sbsc->sdmrtmpcr); - writel(0x00000004, &sbsc->sdmrtmpmsk); - writel(0xa55a0032, &sbsc->rtcor); - writel(0xa55a000c, &sbsc->rtcorh); - writel(0xa55a2048, &sbsc->rtcsr); - writel(readl(&sbsc->sdcr0)|0x800, &sbsc->sdcr0); - writel(readl(&sbsc->sdcr1)|0x400, &sbsc->sdcr1); - writel(0xfff20000, &sbsc->zqccr); - - /* SCBS2 only */ - if (sbsc == (struct sh73a0_sbsc *)SBSC2_BASE) { - writel(readl(&sbsc->sdpdcr0)|0x00030000, &sbsc->sdpdcr0); - writel(0xa5390000, &sbsc->dphycnt1); - writel(0x00001200, &sbsc->dphycnt0); - writel(0x07ce0000, &sbsc->dphycnt1); - writel(0x00001247, &sbsc->dphycnt0); - cmp_loop(&sbsc->dphycnt2, 0xffffffff, 0x07ce0000); - writel(readl(&sbsc->sdpdcr0) & 0xfffcffff, &sbsc->sdpdcr0); - } -} - -void s_init(void) -{ - struct sh73a0_rwdt *rwdt = (struct sh73a0_rwdt *)RWDT_BASE; - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - struct sh73a0_sbsc *sbsc1 = (struct sh73a0_sbsc *)SBSC1_BASE; - struct sh73a0_sbsc *sbsc2 = (struct sh73a0_sbsc *)SBSC2_BASE; - struct sh73a0_hpb *hpb = (struct sh73a0_hpb *)HPB_BASE; - struct sh73a0_hpb_bscr *hpb_bscr = - (struct sh73a0_hpb_bscr *)HPBSCR_BASE; - - /* Watchdog init */ - writew(0xA507, &rwdt->rwtcsra0); - - /* Secure control register Init */ - #define LIFEC_SEC_SRC_BIT (1 << 15) - writel(readl(LIFEC_SEC_SRC) & ~LIFEC_SEC_SRC_BIT, LIFEC_SEC_SRC); - - clrbits_le32(&cpg->smstpcr3, (1 << 15)); - clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); - clrbits_le32(&cpg->smstpcr2, (1 << 18)); - clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); - writel(0x0, &cpg->pllecr); - - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x96235880, &cpg->frqcrb); - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - - writel(0xB, &cpg->flckcr); - clrbits_le32(&cpg->smstpcr0, (1 << 1)); - - clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); - writel(0x0514, &hpb_bscr->smgpiotime); - writel(0x0514, &hpb_bscr->smcmt2time); - writel(0x0514, &hpb_bscr->smcpgtime); - writel(0x0514, &hpb_bscr->smsysctime); - - writel(0x00092000, &cpg->dvfscr4); - writel(0x000000DC, &cpg->dvfscr5); - writel(0x0, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000F00, 0x0); - - /* FRQCR Init */ - writel(0x0012453C, &cpg->frqcra); - writel(0x80431350, &cpg->frqcrb); /* ETM TRCLK 78MHz */ - cmp_loop(&cpg->frqcrb, 0x80000000, 0x0); - writel(0x00000B0B, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - /* Clock Init */ - writel(0x00000003, PCLKCR); - writel(0x0000012F, &cpg->vclkcr1); - writel(0x00000119, &cpg->vclkcr2); - writel(0x00000119, &cpg->vclkcr3); - writel(0x00000002, &cpg->zbckcr); - writel(0x00000005, &cpg->flckcr); - writel(0x00000080, &cpg->sd0ckcr); - writel(0x00000080, &cpg->sd1ckcr); - writel(0x00000080, &cpg->sd2ckcr); - writel(0x0000003F, &cpg->fsiackcr); - writel(0x0000003F, &cpg->fsibckcr); - writel(0x00000080, &cpg->subckcr); - writel(0x0000000B, &cpg->spuackcr); - writel(0x0000000B, &cpg->spuvckcr); - writel(0x0000013F, &cpg->msuckcr); - writel(0x00000080, &cpg->hsickcr); - writel(0x0000003F, &cpg->mfck1cr); - writel(0x0000003F, &cpg->mfck2cr); - writel(0x00000107, &cpg->dsitckcr); - writel(0x00000313, &cpg->dsi0pckcr); - writel(0x0000130D, &cpg->dsi1pckcr); - writel(0x2A800E0E, &cpg->dsi0phycr); - writel(0x1E000000, &cpg->pll0cr); - writel(0x2D000000, &cpg->pll0cr); - writel(0x17100000, &cpg->pll1cr); - writel(0x27000080, &cpg->pll2cr); - writel(0x1D000000, &cpg->pll3cr); - writel(0x00080000, &cpg->pll0stpcr); - writel(0x000120C0, &cpg->pll1stpcr); - writel(0x00012000, &cpg->pll2stpcr); - writel(0x00000030, &cpg->pll3stpcr); - - writel(0x0000000B, &cpg->pllecr); - cmp_loop(&cpg->pllecr, 0x00000B00, 0x00000B00); - - writel(0x000120F0, &cpg->dvfscr3); - writel(0x00000020, &cpg->mpmode); - writel(0x0000028A, &cpg->vrefcr); - writel(0xE4628087, &cpg->rmstpcr0); - writel(0xFFFFFFFF, &cpg->rmstpcr1); - writel(0x53FFFFFF, &cpg->rmstpcr2); - writel(0xFFFFFFFF, &cpg->rmstpcr3); - writel(0x00800D3D, &cpg->rmstpcr4); - writel(0xFFFFF3FF, &cpg->rmstpcr5); - writel(0x00000000, &cpg->smstpcr2); - writel(0x00040000, &cpg_srcr->srcr2); - - clrbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x00000800, 0x0); - - writel(0x00000001, &hpb->hpbctrl6); - cmp_loop(&hpb->hpbctrl6, 0x1, 0x1); - - writel(0x00001414, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - - writel(0x1d000000, &cpg->pll3cr); - setbits_le32(&cpg->pllecr, (1 << 3)); - cmp_loop(&cpg->pllecr, 0x800, 0x800); - - /* SBSC1 Init*/ - sbsc_init(sbsc1); - - /* SBSC2 Init*/ - sbsc_init(sbsc2); - - writel(0x00000b0b, &cpg->frqcrd); - cmp_loop(&cpg->frqcrd, 0x80000000, 0x0); - writel(0xfffffffc, &cpg->cpgxxcs4); -} - -int board_early_init_f(void) -{ - struct sh73a0_sbsc_cpg *cpg = (struct sh73a0_sbsc_cpg *)CPG_BASE; - struct sh73a0_bsc *bsc = (struct sh73a0_bsc *)BSC_BASE; - struct sh73a0_sbsc_cpg_srcr *cpg_srcr = - (struct sh73a0_sbsc_cpg_srcr *)CPG_SRCR_BASE; - - writel(CS0BCR_D, &bsc->cs0bcr); - writel(CS4BCR_D, &bsc->cs4bcr); - writel(CS0WCR_D, &bsc->cs0wcr); - writel(CS4WCR_D, &bsc->cs4wcr); - - clrsetbits_le32(&bsc->cmncr, ~CMNCR_BROMMD, CMNCR_BROMMD); - - clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); - clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); - writel(VCLKCR1_D, &cpg->vclkcr1); - - /* Setup SCIF4 / workaround */ - writeb(0x12, PORT32CR); - writeb(0x22, PORT33CR); - writeb(0x12, PORT34CR); - writeb(0x22, PORT35CR); - - return 0; -} - -void adjust_core_voltage(void) -{ - u8 data; - - data = 0x35; - i2c_set_bus_num(0); - i2c_write(0x40, 3, 1, &data, 1); -} - -int board_init(void) -{ - adjust_core_voltage(); - sh73a0_pinmux_init(); - - /* SCIFA 4 */ - gpio_request(GPIO_FN_SCIFA4_TXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RXD, NULL); - gpio_request(GPIO_FN_SCIFA4_RTS_, NULL); - gpio_request(GPIO_FN_SCIFA4_CTS_, NULL); - - /* Ethernet/SMSC */ - gpio_request(GPIO_PORT224, NULL); - gpio_direction_input(GPIO_PORT224); - - /* SMSC/USB */ - gpio_request(GPIO_FN_CS4_, NULL); - - /* MMCIF */ - gpio_request(GPIO_FN_MMCCLK0, NULL); - gpio_request(GPIO_FN_MMCCMD0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_0_PU, NULL); - gpio_request(GPIO_FN_MMCD0_1_PU, NULL); - gpio_request(GPIO_FN_MMCD0_2_PU, NULL); - gpio_request(GPIO_FN_MMCD0_3_PU, NULL); - gpio_request(GPIO_FN_MMCD0_4_PU, NULL); - gpio_request(GPIO_FN_MMCD0_5_PU, NULL); - gpio_request(GPIO_FN_MMCD0_6_PU, NULL); - gpio_request(GPIO_FN_MMCD0_7_PU, NULL); - - /* SDHI */ - gpio_request(GPIO_FN_SDHIWP0, NULL); - gpio_request(GPIO_FN_SDHICD0, NULL); - gpio_request(GPIO_FN_SDHICMD0, NULL); - gpio_request(GPIO_FN_SDHICLK0, NULL); - gpio_request(GPIO_FN_SDHID0_3, NULL); - gpio_request(GPIO_FN_SDHID0_2, NULL); - gpio_request(GPIO_FN_SDHID0_1, NULL); - gpio_request(GPIO_FN_SDHID0_0, NULL); - gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); - gpio_request(GPIO_PORT15, NULL); - gpio_direction_output(GPIO_PORT15, 1); - - /* I2C */ - gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL); - gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL); - gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL); - gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL); - - gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100); - - return 0; -} - -int dram_init(void) -{ - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - int ret = 0; -#ifdef CONFIG_SMC911X - ret = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return ret; -} - -void reset_cpu(void) -{ - /* Soft Power On Reset */ - writel((1 << 31), RESCNT2); -} diff --git a/configs/kzm9g_defconfig b/configs/kzm9g_defconfig deleted file mode 100644 index 58191c114c54..000000000000 --- a/configs/kzm9g_defconfig +++ /dev/null @@ -1,47 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_CPU_INIT=y -# CONFIG_SYS_THUMB_BUILD is not set -CONFIG_ARCH_RMOBILE=y -CONFIG_SYS_TEXT_BASE=0x00000000 -CONFIG_SYS_MALLOC_LEN=0x60000 -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SIZE=0x40000 -CONFIG_ENV_SECT_SIZE=0x40000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="KMC KZM-A9-GT" -CONFIG_TARGET_KZM9G=y -CONFIG_SYS_LOAD_ADDR=0x43000000 -CONFIG_ENV_ADDR=0x40000 -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="root=/dev/null console=ttySC4,115200" -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -CONFIG_SYS_PROMPT="KZM-A9-GT# " -CONFIG_SYS_CBSIZE=256 -CONFIG_SYS_PBSIZE=256 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_DHCP=y -CONFIG_NFS_TIMEOUT=10000 -CONFIG_CMD_PING=y -CONFIG_CMD_FAT=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_VERSION_VARIABLE=y -CONFIG_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SH=y -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y -CONFIG_SYS_FLASH_EMPTY_INFO=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0x10000000 -CONFIG_SMC911X_32_BIT=y -CONFIG_SCIF_CONSOLE=y -# CONFIG_FAT_WRITE is not set -CONFIG_OF_LIBFDT=y diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h deleted file mode 100644 index 602c1c539190..000000000000 --- a/include/configs/kzm9g.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Nobuhiro Iwamatsu nobuhiro.iwamatsu.yj@renesas.com - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __KZM9G_H -#define __KZM9G_H - -#define CONFIG_SH73A0 - -#include <asm/arch/rmobile.h> - -/* MEMORY */ -#define KZM_SDRAM_BASE (0x40000000) -#define PHYS_SDRAM KZM_SDRAM_BASE -#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) - -/* NOR Flash */ -#define KZM_FLASH_BASE (0x00000000) -#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) - -/* prompt */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ - -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000) -#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) -#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) - -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 - -/* FLASH */ -#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ - -/* Timeout for Flash erase operations (in ms) */ -/* Timeout for Flash write operations (in ms) */ -/* Timeout for Flash set sector lock bit operations (in ms) */ -/* Timeout for Flash clear lock bit operations (in ms) */ - -/* GPIO / PFC */ -#define CONFIG_SH_GPIO_PFC - -/* Clock */ -#define CONFIG_GLOBAL_TIMER -#define CONFIG_SYS_CPU_CLK (1196000000) -#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ - -#endif /* __KZM9G_H */