Re: [U-Boot] [PATCH 7/9] riscv: ax25: Andes specific cache shall only support in M-mode.

Hi Rick,

On Tue, Mar 19, 2019 at 5:12 PM Andes uboot@andestech.com wrote:

From: Rick Chen rick@andestech.com

nits: remove the ending period in the commit title

Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode.

Signed-off-by: Rick Chen rick@andestech.com Cc: Greentime Hu greentime@andestech.com

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arch/riscv/cpu/ax25/Kconfig | 1 + 1 file changed, 1 insertion(+)

Reviewed-by: Bin Meng bmeng.cn@gmail.com

Regards, Bin