Hello Marek,
On Tue, 29 Dec 2015 19:44:01 +0100, Marek Vasut marex@denx.de wrote:
The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly.
The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely.
The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change.
Analysis of the series shows that:
- it does not change the values of DCACHE_OFF, DCACHE_WRITETHROUGH and DCACHE_WRITEBACK;
- it does change the value of DCACHE_WRITEALLOC from 0x16 to 0x101E, but DCACHE_WRITEALLOC is only used when CONFIG_SYS_ARM_CACHE_WRITEALLOC is defined, which does not happen throughout U-Boot, as shown by a search for "WRITEALLOC".
- it sets inner and outer region cache control bits in TTBR0, to match the cacheability of the DDR in which the MMU table resides.
Marek performed tests of patch 1/2 only (with the S bit set) and of the whole series (wih the S bit clear). With patch 1/2 only, Marek could witness the performance hit described by Stefan Roese; with the whole series, Marek saw no performance hit any more.
I will therefore take this patch series in, since it fixes an obvious issue in the U-Boot code and does not show any adverse effect.
Amicalement,