From: Markus Niebel Markus.Niebel@tqs.de
Currently the dual cora variant is detected and displayed as quad core. Add a define for MXC_CPU_MX6DUAL and implement the same SCU based approach done for MX6DL / MX6S
Signed-off-by: Markus Niebel Markus.Niebel@tqs.de --- arch/arm/cpu/armv7/mx6/soc.c | 6 ++++++ arch/arm/imx-common/cpu.c | 2 ++ arch/arm/include/asm/arch-mx5/sys_proto.h | 1 + arch/arm/include/asm/arch-mx6/sys_proto.h | 1 + 4 files changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index a390296..1f65d85 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -42,6 +42,12 @@ u32 get_cpu_rev(void)
if (!cfg) type = MXC_CPU_MX6SOLO; + } else if (type == MXC_CPU_MX6Q) { + struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR; + u32 cfg = readl(&scu->config) & 3; + + if (1 == cfg) + type = MXC_CPU_MX6DUAL; } } reg &= 0xff; /* mx6 silicon revision */ diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 0cd2538..77ef912 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -104,6 +104,8 @@ unsigned imx_ddr_size(void) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_MX6DUAL: + return "6D"; /* Dual-core version of the mx6 */ case MXC_CPU_MX6Q: return "6Q"; /* Quad-core version of the mx6 */ case MXC_CPU_MX6DL: diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 9949ad1..c2bec45 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -14,6 +14,7 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6DUAL 0x64
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void); diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index 8c21364..227998c 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -16,6 +16,7 @@ #define MXC_CPU_MX6DL 0x61 #define MXC_CPU_MX6SOLO 0x62 #define MXC_CPU_MX6Q 0x63 +#define MXC_CPU_MX6DUAL 0x64
#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) u32 get_cpu_rev(void);